| Message ID | 20200512215148.540322-1-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | ARM: dts: meson8b/m2: RGMII improvements | expand |
Hello: This series was applied to khilman/linux-amlogic.git (refs/heads/for-next). On Tue, 12 May 2020 23:51:46 +0200 you wrote: > Hi Kevin, > > the fist patch in this series connects FCLK_DIV2 to the PRG_ETH > "additional" registers for the dwmac Ethernet controller. > Now that we know how RGMII and FCLK_DIV2 are connected we can > add this dependency to get rid of CLK_IS_CRITICAL for FCLK_DIV2 > at some point. > > [...] Here is a summary with links: - [1/2] ARM: dts: meson: Add the Ethernet "timing-adjustment" clock https://git.kernel.org/khilman/linux-amlogic/c/b632506c5af22a9a7c63674fc605d24cf94d585b - [2/2] ARM: dts: meson: Switch existing boards with RGMII PHY to "rgmii-id" https://git.kernel.org/khilman/linux-amlogic/c/005231128e9e97461e81fa32421957a7664317ca You are awesome, thank you!
On Tue, 12 May 2020 23:51:46 +0200, Martin Blumenstingl wrote: > the fist patch in this series connects FCLK_DIV2 to the PRG_ETH > "additional" registers for the dwmac Ethernet controller. > Now that we know how RGMII and FCLK_DIV2 are connected we can > add this dependency to get rid of CLK_IS_CRITICAL for FCLK_DIV2 > at some point. > > The second patch fixes the RX and TX delay. The 4ns TX delay which > we have used so far is incorrect and only worked because we were > using an unsupported clock divider in the PRG_ETH registers. That > divider has been fixed with commit bd6f48546b9c ("net: stmmac: > dwmac-meson8b: Fix the RGMII TX delay on Meson8b/8m2 SoCs"). > Instead of "just" fixing the TX delay we can even do better and > switch to phy-mode = "rgmii-id" to let the PHY generate the RX > and TX delay. However, previously we didn't know that there was > an RX delay applied by the MAC on these boards. Only the additional > information from Jianxin in the other series [0] made us aware > of this. Without the other series there will be a 4ns RX delay > (2ns from the MAC and additional 2ns from the PHY). Due to this > dependency I did not add a Fixes tag, because backporting these > .dts patches without their runtime dependency will break stable > kernels. > > [...] Applied, thanks! [1/2] ARM: dts: meson: Add the Ethernet "timing-adjustment" clock commit: b632506c5af22a9a7c63674fc605d24cf94d585b [2/2] ARM: dts: meson: Switch existing boards with RGMII PHY to "rgmii-id" commit: 005231128e9e97461e81fa32421957a7664317ca Best regards,
Hi Kevin, the fist patch in this series connects FCLK_DIV2 to the PRG_ETH "additional" registers for the dwmac Ethernet controller. Now that we know how RGMII and FCLK_DIV2 are connected we can add this dependency to get rid of CLK_IS_CRITICAL for FCLK_DIV2 at some point. The second patch fixes the RX and TX delay. The 4ns TX delay which we have used so far is incorrect and only worked because we were using an unsupported clock divider in the PRG_ETH registers. That divider has been fixed with commit bd6f48546b9c ("net: stmmac: dwmac-meson8b: Fix the RGMII TX delay on Meson8b/8m2 SoCs"). Instead of "just" fixing the TX delay we can even do better and switch to phy-mode = "rgmii-id" to let the PHY generate the RX and TX delay. However, previously we didn't know that there was an RX delay applied by the MAC on these boards. Only the additional information from Jianxin in the other series [0] made us aware of this. Without the other series there will be a 4ns RX delay (2ns from the MAC and additional 2ns from the PHY). Due to this dependency I did not add a Fixes tag, because backporting these .dts patches without their runtime dependency will break stable kernels. TL;DR: Ethernet TX throughput on my Odroid-C1 improved from <200Mbit/s to >700Mbit/s (measured with iperf3) Dependencies: This series has a runtime dependency on v7 of the series called "dwmac-meson8b Ethernet RX delay configuration" [0] [0] https://patchwork.kernel.org/cover/11543997/ Martin Blumenstingl (2): ARM: dts: meson: Add the Ethernet "timing-adjustment" clock ARM: dts: meson: Switch existing boards with RGMII PHY to "rgmii-id" arch/arm/boot/dts/meson8b-odroidc1.dts | 3 +-- arch/arm/boot/dts/meson8b.dtsi | 5 +++-- arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 4 +--- arch/arm/boot/dts/meson8m2.dtsi | 5 +++-- 4 files changed, 8 insertions(+), 9 deletions(-)