| Message ID | 1589707344-8871-3-git-send-email-tdas@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: Support for Low Power Audio Clocks on SC7180 | expand |
Quoting Taniya Das (2020-05-17 02:22:22) > diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml > new file mode 100644 > index 0000000..c025a0ae > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml > @@ -0,0 +1,101 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm LPASS Core Clock Controller Binding for SC7180 > + > +maintainers: > + - Taniya Das <tdas@codeaurora.org> > + > +description: | > + Qualcomm LPASS core clock control module which supports the clocks and > + power domains on SC7180. > + > + See also: > + - dt-bindings/clock/qcom,lpasscorecc-sc7180.h > + > +properties: > + compatible: > + enum: > + - qcom,sc7180-lpasshm > + - qcom,sc7180-lpasscorecc > + > + clocks: > + items: > + - description: gcc_lpass_sway clock from GCC > + > + clock-names: > + items: > + - const: gcc_lpass_sway As said on patch #4, maybe "iface" instead? > + > + power-domains: > + items: > + - description: LPASS CORE HM GSDCR > +
On Sun, May 17, 2020 at 02:52:22PM +0530, Taniya Das wrote: > The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic > properties that are needed in a device tree. Also add clock ids for GCC > LPASS and LPASS Core clock IDs for LPASS client to request for the clocks. > > Signed-off-by: Taniya Das <tdas@codeaurora.org> > --- > .../bindings/clock/qcom,sc7180-lpasscorecc.yaml | 101 +++++++++++++++++++++ > include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 + > .../dt-bindings/clock/qcom,lpasscorecc-sc7180.h | 29 ++++++ > 3 files changed, 131 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml > create mode 100644 include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml > new file mode 100644 > index 0000000..c025a0ae > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml > @@ -0,0 +1,101 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm LPASS Core Clock Controller Binding for SC7180 > + > +maintainers: > + - Taniya Das <tdas@codeaurora.org> > + > +description: | > + Qualcomm LPASS core clock control module which supports the clocks and > + power domains on SC7180. > + > + See also: > + - dt-bindings/clock/qcom,lpasscorecc-sc7180.h > + > +properties: > + compatible: > + enum: > + - qcom,sc7180-lpasshm > + - qcom,sc7180-lpasscorecc > + > + clocks: > + items: > + - description: gcc_lpass_sway clock from GCC > + > + clock-names: > + items: > + - const: gcc_lpass_sway > + > + power-domains: > + items: > + - description: LPASS CORE HM GSDCR For single entry, 'maxItems: 1' is enough. > + > + '#clock-cells': > + const: 1 > + > + '#power-domain-cells': > + const: 1 > + > + reg: > + minItems: 1 > + maxItems: 2 > + items: > + - description: lpass audio cc register > + - description: lpass core cc register audio then core > + > + reg-names: > + items: > + - const: lpass_core_cc > + - const: lpass_audio_cc core then audio? 2 reg-names required, but 1 reg allowed? > + > +if: > + properties: > + compatible: > + contains: > + const: qcom,sc7180-lpasshm > +then: > + properties: > + reg: > + items: > + - description: lpass hm core register reg-names allowed in this case? Ideally, this would have just 'maxItems: 1' to just disallow the 2nd entry above. > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - '#clock-cells' > + - '#power-domain-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-sc7180.h> > + #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> > + clock-controller@63000000 { > + compatible = "qcom,sc7180-lpasshm"; > + reg = <0 0x63000000 0 0x28>; > + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; > + clock-names = "gcc_lpass_sway"; > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + - | > + clock-controller@62d00000 { > + compatible = "qcom,sc7180-lpasscorecc"; > + reg = <0 0x62d00000 0 0x50000>, > + <0 0x62780000 0 0x30000>; > + reg-names = "lpass_core_cc", "lpass_audio_cc"; > + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; > + clock-names = "gcc_lpass_sway"; > + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; > + #clock-cells = <1>; > + #power-domain-cells = <1>; > + }; > +... > diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h > index 1258fd0..439476c 100644 > --- a/include/dt-bindings/clock/qcom,gcc-sc7180.h > +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h > @@ -137,6 +137,7 @@ > #define GCC_MSS_NAV_AXI_CLK 127 > #define GCC_MSS_Q6_MEMNOC_AXI_CLK 128 > #define GCC_MSS_SNOC_AXI_CLK 129 > +#define GCC_LPASS_CFG_NOC_SWAY_CLK 130 > > /* GCC resets */ > #define GCC_QUSB2PHY_PRIM_BCR 0 > diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h > new file mode 100644 > index 0000000..a55d01d > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h > @@ -0,0 +1,29 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2020, The Linux Foundation. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H > +#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H > + > +/* LPASS_CORE_CC clocks */ > +#define LPASS_LPAAUDIO_DIG_PLL 0 > +#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1 > +#define CORE_CLK_SRC 2 > +#define EXT_MCLK0_CLK_SRC 3 > +#define LPAIF_PRI_CLK_SRC 4 > +#define LPAIF_SEC_CLK_SRC 5 > +#define LPASS_AUDIO_CORE_CORE_CLK 6 > +#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7 > +#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8 > +#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9 > +#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10 > + > +/* LPASS Core power domains */ > +#define LPASS_CORE_HM_GDSCR 0 > + > +/* LPASS Audio power domains */ > +#define LPASS_AUDIO_HM_GDSCR 0 > +#define LPASS_PDC_HM_GDSCR 1 > + > +#endif > -- > Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member > of the Code Aurora Forum, hosted by the Linux Foundation. >
Thanks for the review. On 5/27/2020 8:41 AM, Stephen Boyd wrote: >> + clocks: >> + items: >> + - description: gcc_lpass_sway clock from GCC >> + >> + clock-names: >> + items: >> + - const: gcc_lpass_sway > > As said on patch #4, maybe "iface" instead? > Will take care in the next patch. >> + >> + power-domains: >> + items: >> + - description: LPASS CORE HM GSDCR >> +
Thanks for your review. On 5/29/2020 1:55 AM, Rob Herring wrote: > On Sun, May 17, 2020 at 02:52:22PM +0530, Taniya Das wrote: >> The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic >> properties that are needed in a device tree. Also add clock ids for GCC >> LPASS and LPASS Core clock IDs for LPASS client to request for the clocks. >> >> Signed-off-by: Taniya Das <tdas@codeaurora.org> >> --- >> .../bindings/clock/qcom,sc7180-lpasscorecc.yaml | 101 +++++++++++++++++++++ >> include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 + >> .../dt-bindings/clock/qcom,lpasscorecc-sc7180.h | 29 ++++++ >> 3 files changed, 131 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml >> create mode 100644 include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml >> new file mode 100644 >> index 0000000..c025a0ae >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml >> @@ -0,0 +1,101 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm LPASS Core Clock Controller Binding for SC7180 >> + >> +maintainers: >> + - Taniya Das <tdas@codeaurora.org> >> + >> +description: | >> + Qualcomm LPASS core clock control module which supports the clocks and >> + power domains on SC7180. >> + >> + See also: >> + - dt-bindings/clock/qcom,lpasscorecc-sc7180.h >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,sc7180-lpasshm >> + - qcom,sc7180-lpasscorecc >> + >> + clocks: >> + items: >> + - description: gcc_lpass_sway clock from GCC >> + >> + clock-names: >> + items: >> + - const: gcc_lpass_sway >> + >> + power-domains: >> + items: >> + - description: LPASS CORE HM GSDCR > > For single entry, 'maxItems: 1' is enough. Will take of it in the next patch. >> + >> + '#clock-cells': >> + const: 1 >> + >> + '#power-domain-cells': >> + const: 1 >> + >> + reg: >> + minItems: 1 >> + maxItems: 2 >> + items: >> + - description: lpass audio cc register >> + - description: lpass core cc register > > audio then core > >> + >> + reg-names: >> + items: >> + - const: lpass_core_cc >> + - const: lpass_audio_cc > > core then audio? > My bad, will take care of it. > 2 reg-names required, but 1 reg allowed? > Update to use maxItems: 2 in the next patch. >> + >> +if: >> + properties: >> + compatible: >> + contains: >> + const: qcom,sc7180-lpasshm >> +then: >> + properties: >> + reg: >> + items: >> + - description: lpass hm core register > > reg-names allowed in this case? > > Ideally, this would have just 'maxItems: 1' to just disallow the 2nd > entry above. > Yes, I would take care of this too. >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - '#clock-cells' >> + - '#power-domain-cells' >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include <dt-bindings/clock/qcom,gcc-sc7180.h> >> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> >> + clock-controller@63000000 { >> + compatible = "qcom,sc7180-lpasshm"; >> + reg = <0 0x63000000 0 0x28>; >> + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; >> + clock-names = "gcc_lpass_sway"; >> + #clock-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> + - | >> + clock-controller@62d00000 { >> + compatible = "qcom,sc7180-lpasscorecc"; >> + reg = <0 0x62d00000 0 0x50000>, >> + <0 0x62780000 0 0x30000>; >> + reg-names = "lpass_core_cc", "lpass_audio_cc"; >> + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; >> + clock-names = "gcc_lpass_sway"; >> + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; >> + #clock-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> +... >> diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h >> index 1258fd0..439476c 100644 >> --- a/include/dt-bindings/clock/qcom,gcc-sc7180.h >> +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h >> @@ -137,6 +137,7 @@ >> #define GCC_MSS_NAV_AXI_CLK 127 >> #define GCC_MSS_Q6_MEMNOC_AXI_CLK 128 >> #define GCC_MSS_SNOC_AXI_CLK 129 >> +#define GCC_LPASS_CFG_NOC_SWAY_CLK 130 >> >> /* GCC resets */ >> #define GCC_QUSB2PHY_PRIM_BCR 0 >> diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h >> new file mode 100644 >> index 0000000..a55d01d >> --- /dev/null >> +++ b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h >> @@ -0,0 +1,29 @@ >> +/* SPDX-License-Identifier: GPL-2.0-only */ >> +/* >> + * Copyright (c) 2020, The Linux Foundation. All rights reserved. >> + */ >> + >> +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H >> +#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H >> + >> +/* LPASS_CORE_CC clocks */ >> +#define LPASS_LPAAUDIO_DIG_PLL 0 >> +#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1 >> +#define CORE_CLK_SRC 2 >> +#define EXT_MCLK0_CLK_SRC 3 >> +#define LPAIF_PRI_CLK_SRC 4 >> +#define LPAIF_SEC_CLK_SRC 5 >> +#define LPASS_AUDIO_CORE_CORE_CLK 6 >> +#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7 >> +#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8 >> +#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9 >> +#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10 >> + >> +/* LPASS Core power domains */ >> +#define LPASS_CORE_HM_GDSCR 0 >> + >> +/* LPASS Audio power domains */ >> +#define LPASS_AUDIO_HM_GDSCR 0 >> +#define LPASS_PDC_HM_GDSCR 1 >> + >> +#endif >> -- >> Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member >> of the Code Aurora Forum, hosted by the Linux Foundation. >>
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml new file mode 100644 index 0000000..c025a0ae --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS Core Clock Controller Binding for SC7180 + +maintainers: + - Taniya Das <tdas@codeaurora.org> + +description: | + Qualcomm LPASS core clock control module which supports the clocks and + power domains on SC7180. + + See also: + - dt-bindings/clock/qcom,lpasscorecc-sc7180.h + +properties: + compatible: + enum: + - qcom,sc7180-lpasshm + - qcom,sc7180-lpasscorecc + + clocks: + items: + - description: gcc_lpass_sway clock from GCC + + clock-names: + items: + - const: gcc_lpass_sway + + power-domains: + items: + - description: LPASS CORE HM GSDCR + + '#clock-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + minItems: 1 + maxItems: 2 + items: + - description: lpass audio cc register + - description: lpass core cc register + + reg-names: + items: + - const: lpass_core_cc + - const: lpass_audio_cc + +if: + properties: + compatible: + contains: + const: qcom,sc7180-lpasshm +then: + properties: + reg: + items: + - description: lpass hm core register + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sc7180.h> + #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> + clock-controller@63000000 { + compatible = "qcom,sc7180-lpasshm"; + reg = <0 0x63000000 0 0x28>; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; + clock-names = "gcc_lpass_sway"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + - | + clock-controller@62d00000 { + compatible = "qcom,sc7180-lpasscorecc"; + reg = <0 0x62d00000 0 0x50000>, + <0 0x62780000 0 0x30000>; + reg-names = "lpass_core_cc", "lpass_audio_cc"; + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>; + clock-names = "gcc_lpass_sway"; + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h b/include/dt-bindings/clock/qcom,gcc-sc7180.h index 1258fd0..439476c 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc7180.h +++ b/include/dt-bindings/clock/qcom,gcc-sc7180.h @@ -137,6 +137,7 @@ #define GCC_MSS_NAV_AXI_CLK 127 #define GCC_MSS_Q6_MEMNOC_AXI_CLK 128 #define GCC_MSS_SNOC_AXI_CLK 129 +#define GCC_LPASS_CFG_NOC_SWAY_CLK 130 /* GCC resets */ #define GCC_QUSB2PHY_PRIM_BCR 0 diff --git a/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h new file mode 100644 index 0000000..a55d01d --- /dev/null +++ b/include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H + +/* LPASS_CORE_CC clocks */ +#define LPASS_LPAAUDIO_DIG_PLL 0 +#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1 +#define CORE_CLK_SRC 2 +#define EXT_MCLK0_CLK_SRC 3 +#define LPAIF_PRI_CLK_SRC 4 +#define LPAIF_SEC_CLK_SRC 5 +#define LPASS_AUDIO_CORE_CORE_CLK 6 +#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7 +#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8 +#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9 +#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10 + +/* LPASS Core power domains */ +#define LPASS_CORE_HM_GDSCR 0 + +/* LPASS Audio power domains */ +#define LPASS_AUDIO_HM_GDSCR 0 +#define LPASS_PDC_HM_GDSCR 1 + +#endif
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for GCC LPASS and LPASS Core clock IDs for LPASS client to request for the clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> --- .../bindings/clock/qcom,sc7180-lpasscorecc.yaml | 101 +++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 + .../dt-bindings/clock/qcom,lpasscorecc-sc7180.h | 29 ++++++ 3 files changed, 131 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml create mode 100644 include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.