| Message ID | 20200602154839.6902-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/gt: Make the CTX_TIMESTAMP readable on !rcs | expand |
On Tue, 2020-06-02 at 16:48 +0100, Chris Wilson wrote: > For reasons that be, the HW only allows usersace to read its own > CTX_TIMESTAMP [context local HW runtime] on rcs. Make it available for > all by adding it to the whitelists. > > v2: The change took effect from Cometlake. > v3: Ignore timestamps that autoincrement when validating the whitelist I would have separated add the register to the whitelist from the selftest but anyways looks good. Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++- > .../gpu/drm/i915/gt/selftest_workarounds.c | 17 +++++++++++++ > 2 files changed, 41 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 6e1accbcc045..0731bbcef06c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1206,6 +1206,18 @@ static void cfl_whitelist_build(struct intel_engine_cs *engine) > RING_FORCE_TO_NONPRIV_RANGE_4); > } > > +static void cml_whitelist_build(struct intel_engine_cs *engine) > +{ > + struct i915_wa_list *w = &engine->whitelist; > + > + if (engine->class != RENDER_CLASS) > + whitelist_reg_ext(w, > + RING_CTX_TIMESTAMP(engine->mmio_base), > + RING_FORCE_TO_NONPRIV_ACCESS_RD); > + > + cfl_whitelist_build(engine); > +} > + > static void cnl_whitelist_build(struct intel_engine_cs *engine) > { > struct i915_wa_list *w = &engine->whitelist; > @@ -1256,9 +1268,15 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) > /* hucStatus2RegOffset */ > whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), > RING_FORCE_TO_NONPRIV_ACCESS_RD); > + whitelist_reg_ext(w, > + RING_CTX_TIMESTAMP(engine->mmio_base), > + RING_FORCE_TO_NONPRIV_ACCESS_RD); > break; > > default: > + whitelist_reg_ext(w, > + RING_CTX_TIMESTAMP(engine->mmio_base), > + RING_FORCE_TO_NONPRIV_ACCESS_RD); > break; > } > } > @@ -1290,6 +1308,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) > whitelist_reg(w, HIZ_CHICKEN); > break; > default: > + whitelist_reg_ext(w, > + RING_CTX_TIMESTAMP(engine->mmio_base), > + RING_FORCE_TO_NONPRIV_ACCESS_RD); > break; > } > } > @@ -1307,7 +1328,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) > icl_whitelist_build(engine); > else if (IS_CANNONLAKE(i915)) > cnl_whitelist_build(engine); > - else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) > + else if (IS_COMETLAKE(i915)) > + cml_whitelist_build(engine); > + else if (IS_COFFEELAKE(i915)) > cfl_whitelist_build(engine); > else if (IS_GEMINILAKE(i915)) > glk_whitelist_build(engine); > diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c > index 32785463ec9e..febc9e6692ba 100644 > --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c > @@ -417,6 +417,20 @@ static bool wo_register(struct intel_engine_cs *engine, u32 reg) > return false; > } > > +static bool timestamp(const struct intel_engine_cs *engine, u32 reg) > +{ > + reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK; > + switch (reg) { > + case 0x358: > + case 0x35c: > + case 0x3a8: > + return true; > + > + default: > + return false; > + } > +} > + > static bool ro_register(u32 reg) > { > if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == > @@ -497,6 +511,9 @@ static int check_dirty_whitelist(struct intel_context *ce) > if (wo_register(engine, reg)) > continue; > > + if (timestamp(engine, reg)) > + continue; /* timestamps are expected to autoincrement */ > + > ro_reg = ro_register(reg); > > /* Clear non priv flags */
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 6e1accbcc045..0731bbcef06c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1206,6 +1206,18 @@ static void cfl_whitelist_build(struct intel_engine_cs *engine) RING_FORCE_TO_NONPRIV_RANGE_4); } +static void cml_whitelist_build(struct intel_engine_cs *engine) +{ + struct i915_wa_list *w = &engine->whitelist; + + if (engine->class != RENDER_CLASS) + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); + + cfl_whitelist_build(engine); +} + static void cnl_whitelist_build(struct intel_engine_cs *engine) { struct i915_wa_list *w = &engine->whitelist; @@ -1256,9 +1268,15 @@ static void icl_whitelist_build(struct intel_engine_cs *engine) /* hucStatus2RegOffset */ whitelist_reg_ext(w, _MMIO(0x23B0 + engine->mmio_base), RING_FORCE_TO_NONPRIV_ACCESS_RD); + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; default: + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; } } @@ -1290,6 +1308,9 @@ static void tgl_whitelist_build(struct intel_engine_cs *engine) whitelist_reg(w, HIZ_CHICKEN); break; default: + whitelist_reg_ext(w, + RING_CTX_TIMESTAMP(engine->mmio_base), + RING_FORCE_TO_NONPRIV_ACCESS_RD); break; } } @@ -1307,7 +1328,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) icl_whitelist_build(engine); else if (IS_CANNONLAKE(i915)) cnl_whitelist_build(engine); - else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) + else if (IS_COMETLAKE(i915)) + cml_whitelist_build(engine); + else if (IS_COFFEELAKE(i915)) cfl_whitelist_build(engine); else if (IS_GEMINILAKE(i915)) glk_whitelist_build(engine); diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c index 32785463ec9e..febc9e6692ba 100644 --- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c +++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c @@ -417,6 +417,20 @@ static bool wo_register(struct intel_engine_cs *engine, u32 reg) return false; } +static bool timestamp(const struct intel_engine_cs *engine, u32 reg) +{ + reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK; + switch (reg) { + case 0x358: + case 0x35c: + case 0x3a8: + return true; + + default: + return false; + } +} + static bool ro_register(u32 reg) { if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) == @@ -497,6 +511,9 @@ static int check_dirty_whitelist(struct intel_context *ce) if (wo_register(engine, reg)) continue; + if (timestamp(engine, reg)) + continue; /* timestamps are expected to autoincrement */ + ro_reg = ro_register(reg); /* Clear non priv flags */
For reasons that be, the HW only allows usersace to read its own CTX_TIMESTAMP [context local HW runtime] on rcs. Make it available for all by adding it to the whitelists. v2: The change took effect from Cometlake. v3: Ignore timestamps that autoincrement when validating the whitelist Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 25 ++++++++++++++++++- .../gpu/drm/i915/gt/selftest_workarounds.c | 17 +++++++++++++ 2 files changed, 41 insertions(+), 1 deletion(-)