| Message ID | 1591701165-12872-2-git-send-email-jun.li@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add NXP imx8mp usb support | expand |
On 20-06-09 19:12:40, Li Jun wrote: > Add a property "snps,xhci-dis-64bit-support-quirk" to disable xhci 64bit > address support, this is due to SoC integration can't support it but > the AC64 bit (bit 0) of HCCPARAMS1 is set to be 1. > > Signed-off-by: Li Jun <jun.li@nxp.com> > --- > Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt > index d03edf9..d16cba7 100644 > --- a/Documentation/devicetree/bindings/usb/dwc3.txt > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt > @@ -109,6 +109,9 @@ Optional properties: > When just one value, which means INCRX burst mode enabled. When > more than one value, which means undefined length INCR burst type > enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. > + - snps,xhci-dis-64bit-support-quirk: set if the AC64 bit (bit 0) of HCCPARAMS1 is set > + to be 1, but the controller actually can't handle 64-bit address > + due to SoC integration. > > - in addition all properties from usb-xhci.txt from the current directory are > supported as well Why not adding it at usb-xhci.txt directly? It is more like general property, I see Renesas rcar platforms also have this quirk.
On 6/9/2020 7:47 PM, Peter Chen wrote: > On 20-06-09 19:12:40, Li Jun wrote: >> Add a property "snps,xhci-dis-64bit-support-quirk" to disable xhci 64bit >> address support, this is due to SoC integration can't support it but >> the AC64 bit (bit 0) of HCCPARAMS1 is set to be 1. >> >> Signed-off-by: Li Jun <jun.li@nxp.com> >> --- >> Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt >> index d03edf9..d16cba7 100644 >> --- a/Documentation/devicetree/bindings/usb/dwc3.txt >> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt >> @@ -109,6 +109,9 @@ Optional properties: >> When just one value, which means INCRX burst mode enabled. When >> more than one value, which means undefined length INCR burst type >> enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. >> + - snps,xhci-dis-64bit-support-quirk: set if the AC64 bit (bit 0) of HCCPARAMS1 is set >> + to be 1, but the controller actually can't handle 64-bit address >> + due to SoC integration. >> >> - in addition all properties from usb-xhci.txt from the current directory are >> supported as well > > Why not adding it at usb-xhci.txt directly? It is more like general > property, I see Renesas rcar platforms also have this quirk. > Or rather define a compatible string for the specific SoC integration here and based upon that compatibility string set the xhci->quirks to have XHCI_NO_64BIT_SUPPORT set.
> -----Original Message----- > From: Florian Fainelli <f.fainelli@gmail.com> > Sent: Wednesday, June 10, 2020 12:22 PM > To: Peter Chen <peter.chen@nxp.com>; Jun Li <jun.li@nxp.com> > Cc: balbi@kernel.org; festevam@gmail.com; gregkh@linuxfoundation.org; > s.hauer@pengutronix.de; linux-usb@vger.kernel.org; robh+dt@kernel.org; > dl-linux-imx <linux-imx@nxp.com>; kernel@pengutronix.de; shawnguo@kernel.org; > linux-arm-kernel@lists.infradead.org > Subject: Re: [PATCH 1/6] dt-bindings: usb: dwc3: add property to disable xhci 64bit > support > > > > On 6/9/2020 7:47 PM, Peter Chen wrote: > > On 20-06-09 19:12:40, Li Jun wrote: > >> Add a property "snps,xhci-dis-64bit-support-quirk" to disable xhci > >> 64bit address support, this is due to SoC integration can't support > >> it but the AC64 bit (bit 0) of HCCPARAMS1 is set to be 1. > >> > >> Signed-off-by: Li Jun <jun.li@nxp.com> > >> --- > >> Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++ > >> 1 file changed, 3 insertions(+) > >> > >> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt > >> b/Documentation/devicetree/bindings/usb/dwc3.txt > >> index d03edf9..d16cba7 100644 > >> --- a/Documentation/devicetree/bindings/usb/dwc3.txt > >> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt > >> @@ -109,6 +109,9 @@ Optional properties: > >> When just one value, which means INCRX burst mode enabled. When > >> more than one value, which means undefined length INCR burst type > >> enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. > >> + - snps,xhci-dis-64bit-support-quirk: set if the AC64 bit (bit 0) of HCCPARAMS1 > is set > >> + to be 1, but the controller actually can't handle 64-bit address > >> + due to SoC integration. > >> > >> - in addition all properties from usb-xhci.txt from the current directory are > >> supported as well > > > > Why not adding it at usb-xhci.txt directly? It is more like general > > property, I see Renesas rcar platforms also have this quirk. > > > > Or rather define a compatible string for the specific SoC integration here and based > upon that compatibility string set the xhci->quirks to have XHCI_NO_64BIT_SUPPORT > set. Hi Florian, Peter Sent out v2 with changes to use platform data so compatible string based to pass those xhci quirks to xhci-plat. Thanks Li Jun > -- > Florian
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index d03edf9..d16cba7 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -109,6 +109,9 @@ Optional properties: When just one value, which means INCRX burst mode enabled. When more than one value, which means undefined length INCR burst type enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. + - snps,xhci-dis-64bit-support-quirk: set if the AC64 bit (bit 0) of HCCPARAMS1 is set + to be 1, but the controller actually can't handle 64-bit address + due to SoC integration. - in addition all properties from usb-xhci.txt from the current directory are supported as well
Add a property "snps,xhci-dis-64bit-support-quirk" to disable xhci 64bit address support, this is due to SoC integration can't support it but the AC64 bit (bit 0) of HCCPARAMS1 is set to be 1. Signed-off-by: Li Jun <jun.li@nxp.com> --- Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++ 1 file changed, 3 insertions(+)