mbox series

[0/6] Add several Power ISA 3.1 32/64-bit vector instructions

Message ID 20200613042029.22321-1-ljp@linux.ibm.com (mailing list archive)
Headers show
Series Add several Power ISA 3.1 32/64-bit vector instructions | expand

Message

Lijun Pan June 13, 2020, 4:20 a.m. UTC 
This patch series add several newly introduced 32/64-bit vector
instructions in Power ISA 3.1. The newly added instructions are
flagged as ISA300 temporarily in vmx-ops.inc.c and vmx-impl.inc.c
to make them compile and function since Power ISA 3.1, together
with next generation processor, has not been fully enabled in QEMU
yet. When Power ISA 3.1 and next generation processor are fully
supported, the flags should be changed.

Lijun Pan (6):
  target/ppc: add byte-reverse br[dwh] instructions
  target/ppc: add vmulld instruction
  targetc/ppc: add vmulh{su}w instructions
  target/ppc: add vmulh{su}d instructions
  fix the prototype of muls64/mulu64
  target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions

 include/qemu/host-utils.h           |  4 +-
 target/ppc/helper.h                 | 13 ++++++
 target/ppc/int_helper.c             | 58 +++++++++++++++++++++++++
 target/ppc/translate.c              | 65 +++++++++++++++++++++++++++++
 target/ppc/translate/vmx-impl.inc.c | 24 +++++++++++
 target/ppc/translate/vmx-ops.inc.c  | 22 ++++++++--
 6 files changed, 180 insertions(+), 6 deletions(-)

Comments

no-reply@patchew.org June 13, 2020, 4:47 a.m. UTC | #1 
Patchew URL: https://patchew.org/QEMU/20200613042029.22321-1-ljp@linux.ibm.com/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20200613042029.22321-1-ljp@linux.ibm.com
Subject: [PATCH 0/6] Add several Power ISA 3.1 32/64-bit vector instructions
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Switched to a new branch 'test'
d39f30e target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions
966b641 fix the prototype of muls64/mulu64
42111c5 target/ppc: add vmulh{su}d instructions
c96e996 targetc/ppc: add vmulh{su}w instructions
c52004c target/ppc: add vmulld instruction
1061e4e target/ppc: add byte-reverse br[dwh] instructions

=== OUTPUT BEGIN ===
1/6 Checking commit 1061e4ead5bc (target/ppc: add byte-reverse br[dwh] instructions)
ERROR: code indent should never use tabs
#26: FILE: target/ppc/translate.c:6977:
+^ITCGv_i64 temp = tcg_temp_new_i64();$

ERROR: code indent should never use tabs
#28: FILE: target/ppc/translate.c:6979:
+^Itcg_gen_bswap64_i64(temp, cpu_gpr[rS(ctx->opcode)]);$

WARNING: line over 80 characters
#29: FILE: target/ppc/translate.c:6980:
+       tcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)]));

ERROR: code indent should never use tabs
#29: FILE: target/ppc/translate.c:6980:
+^Itcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)]));$

ERROR: code indent should never use tabs
#31: FILE: target/ppc/translate.c:6982:
+^Itcg_temp_free_i64(temp);$

ERROR: code indent should never use tabs
#37: FILE: target/ppc/translate.c:6988:
+^ITCGv_i64 temp = tcg_temp_new_i64();$

ERROR: code indent should never use tabs
#38: FILE: target/ppc/translate.c:6989:
+^ITCGv_i64 lsb = tcg_temp_new_i64();$

ERROR: code indent should never use tabs
#39: FILE: target/ppc/translate.c:6990:
+^ITCGv_i64 msb = tcg_temp_new_i64();$

ERROR: code indent should never use tabs
#41: FILE: target/ppc/translate.c:6992:
+^Itcg_gen_movi_i64(lsb, 0x00000000ffffffffull);$

ERROR: code indent should never use tabs
#42: FILE: target/ppc/translate.c:6993:
+^Itcg_gen_and_i64(temp, lsb, cpu_gpr[rS(ctx->opcode)]);$

ERROR: code indent should never use tabs
#43: FILE: target/ppc/translate.c:6994:
+^Itcg_gen_bswap32_i64(lsb, temp);$

ERROR: trailing whitespace
#44: FILE: target/ppc/translate.c:6995:
+^I$

ERROR: code indent should never use tabs
#44: FILE: target/ppc/translate.c:6995:
+^I$

ERROR: code indent should never use tabs
#45: FILE: target/ppc/translate.c:6996:
+^Itcg_gen_shri_i64(msb, cpu_gpr[rS(ctx->opcode)], 32);$

ERROR: code indent should never use tabs
#46: FILE: target/ppc/translate.c:6997:
+^Itcg_gen_bswap32_i64(temp, msb);$

ERROR: code indent should never use tabs
#47: FILE: target/ppc/translate.c:6998:
+^Itcg_gen_shli_i64(msb, temp, 32);$

ERROR: trailing whitespace
#48: FILE: target/ppc/translate.c:6999:
+^I$

ERROR: code indent should never use tabs
#48: FILE: target/ppc/translate.c:6999:
+^I$

ERROR: code indent should never use tabs
#49: FILE: target/ppc/translate.c:7000:
+^Itcg_gen_or_i64(temp, lsb, msb);$

WARNING: line over 80 characters
#51: FILE: target/ppc/translate.c:7002:
+       tcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)]));

ERROR: code indent should never use tabs
#51: FILE: target/ppc/translate.c:7002:
+^Itcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)]));$

ERROR: code indent should never use tabs
#53: FILE: target/ppc/translate.c:7004:
+^Itcg_temp_free_i64(temp);$

ERROR: code indent should never use tabs
#54: FILE: target/ppc/translate.c:7005:
+^Itcg_temp_free_i64(lsb);$

ERROR: code indent should never use tabs
#55: FILE: target/ppc/translate.c:7006:
+^Itcg_temp_free_i64(msb);$

ERROR: code indent should never use tabs
#61: FILE: target/ppc/translate.c:7012:
+^ITCGv_i64 temp = tcg_temp_new_i64();$

ERROR: code indent should never use tabs
#62: FILE: target/ppc/translate.c:7013:
+^ITCGv_i64 t0 = tcg_temp_new_i64();$

ERROR: code indent should never use tabs
#63: FILE: target/ppc/translate.c:7014:
+^ITCGv_i64 t1 = tcg_temp_new_i64();$

ERROR: code indent should never use tabs
#64: FILE: target/ppc/translate.c:7015:
+^ITCGv_i64 t2 = tcg_temp_new_i64();$

ERROR: code indent should never use tabs
#65: FILE: target/ppc/translate.c:7016:
+^ITCGv_i64 t3 = tcg_temp_new_i64();$

ERROR: code indent should never use tabs
#67: FILE: target/ppc/translate.c:7018:
+^Itcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);$

ERROR: code indent should never use tabs
#68: FILE: target/ppc/translate.c:7019:
+^Itcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);$

ERROR: code indent should never use tabs
#69: FILE: target/ppc/translate.c:7020:
+^Itcg_gen_and_i64(t2, t1, t0);$

ERROR: code indent should never use tabs
#70: FILE: target/ppc/translate.c:7021:
+^Itcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0);$

ERROR: code indent should never use tabs
#71: FILE: target/ppc/translate.c:7022:
+^Itcg_gen_shli_i64(t1, t1, 8);$

ERROR: code indent should never use tabs
#72: FILE: target/ppc/translate.c:7023:
+^Itcg_gen_or_i64(temp, t1, t2);$

WARNING: line over 80 characters
#73: FILE: target/ppc/translate.c:7024:
+       tcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)]));

ERROR: code indent should never use tabs
#73: FILE: target/ppc/translate.c:7024:
+^Itcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)]));$

ERROR: code indent should never use tabs
#75: FILE: target/ppc/translate.c:7026:
+^Itcg_temp_free_i64(temp);$

ERROR: code indent should never use tabs
#76: FILE: target/ppc/translate.c:7027:
+^Itcg_temp_free_i64(t0);$

ERROR: code indent should never use tabs
#77: FILE: target/ppc/translate.c:7028:
+^Itcg_temp_free_i64(t1);$

ERROR: code indent should never use tabs
#78: FILE: target/ppc/translate.c:7029:
+^Itcg_temp_free_i64(t2);$

ERROR: code indent should never use tabs
#79: FILE: target/ppc/translate.c:7030:
+^Itcg_temp_free_i64(t3);$

total: 39 errors, 3 warnings, 69 lines checked

Patch 1/6 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

2/6 Checking commit c52004cd8f89 (target/ppc: add vmulld instruction)
3/6 Checking commit c96e996917c6 (targetc/ppc: add vmulh{su}w instructions)
ERROR: code indent should never use tabs
#34: FILE: target/ppc/int_helper.c:526:
+#define VMULH_DO(name, op, element, cast_orig, cast_temp)^I^I\$

ERROR: code indent should never use tabs
#35: FILE: target/ppc/int_helper.c:527:
+    void helper_vmulh##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)^I\$

ERROR: code indent should never use tabs
#36: FILE: target/ppc/int_helper.c:528:
+    {^I^I^I^I^I^I^I^I^I\$

ERROR: code indent should never use tabs
#37: FILE: target/ppc/int_helper.c:529:
+^Iint i;^I^I^I^I^I^I^I^I\$

ERROR: code indent should never use tabs
#38: FILE: target/ppc/int_helper.c:530:
+^I^I^I^I^I^I^I^I^I\$

ERROR: code indent should never use tabs
#39: FILE: target/ppc/int_helper.c:531:
+^Ifor (i = 0; i < ARRAY_SIZE(r->element); i++) {^I^I^I\$

ERROR: code indent should never use tabs
#40: FILE: target/ppc/int_helper.c:532:
+^I^Ir->element[i] = (cast_orig)(((cast_temp)a->element[i] op \$

ERROR: code indent should never use tabs
#41: FILE: target/ppc/int_helper.c:533:
+^I^I^I^I(cast_temp)b->element[i]) >> 32);^I\$

ERROR: code indent should never use tabs
#42: FILE: target/ppc/int_helper.c:534:
+^I}^I^I^I^I^I^I^I^I\$

ERROR: code indent should never use tabs
#61: FILE: target/ppc/translate/vmx-impl.inc.c:816:
+^I^Ivmulhuw, PPC_NONE, PPC2_ISA300);$

ERROR: code indent should never use tabs
#67: FILE: target/ppc/translate/vmx-impl.inc.c:822:
+^I^Ivmulhsw, PPC_NONE, PPC2_ISA300);$

total: 11 errors, 0 warnings, 55 lines checked

Patch 3/6 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

4/6 Checking commit 42111c50379b (target/ppc: add vmulh{su}d instructions)
ERROR: code indent should never use tabs
#36: FILE: target/ppc/int_helper.c:528:
+^Iint i;$

ERROR: code indent should never use tabs
#37: FILE: target/ppc/int_helper.c:529:
+^Iuint64_t h64 = 0;$

ERROR: code indent should never use tabs
#38: FILE: target/ppc/int_helper.c:530:
+^Iuint64_t l64 = 0;$

ERROR: code indent should never use tabs
#40: FILE: target/ppc/int_helper.c:532:
+^Ifor (i = 0; i < 2; i++) {$

ERROR: code indent should never use tabs
#41: FILE: target/ppc/int_helper.c:533:
+^I^Imuls64(&l64, &h64, a->s64[i], b->s64[i]);$

ERROR: code indent should never use tabs
#42: FILE: target/ppc/int_helper.c:534:
+^I^Ir->s64[i] = h64;$

ERROR: code indent should never use tabs
#43: FILE: target/ppc/int_helper.c:535:
+^I}$

ERROR: code indent should never use tabs
#48: FILE: target/ppc/int_helper.c:540:
+^Iint i;$

ERROR: code indent should never use tabs
#49: FILE: target/ppc/int_helper.c:541:
+^Iuint64_t h64 = 0;$

ERROR: code indent should never use tabs
#50: FILE: target/ppc/int_helper.c:542:
+^Iuint64_t l64 = 0;$

ERROR: code indent should never use tabs
#52: FILE: target/ppc/int_helper.c:544:
+^Ifor (i = 0; i < 2; i++) {$

ERROR: code indent should never use tabs
#53: FILE: target/ppc/int_helper.c:545:
+^I^Imulu64(&l64, &h64, a->s64[i], b->s64[i]);$

ERROR: code indent should never use tabs
#54: FILE: target/ppc/int_helper.c:546:
+^I^Ir->u64[i] = h64;$

ERROR: code indent should never use tabs
#55: FILE: target/ppc/int_helper.c:547:
+^I}$

total: 14 errors, 0 warnings, 63 lines checked

Patch 4/6 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

5/6 Checking commit 966b641eba85 (fix the prototype of muls64/mulu64)
6/6 Checking commit d39f30e2a46f (target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions)
ERROR: code indent should never use tabs
#104: FILE: target/ppc/translate/vmx-impl.inc.c:832:
+^I^Ivdivsw, PPC_NONE, PPC2_ISA300, 0x00000000);$

ERROR: code indent should never use tabs
#107: FILE: target/ppc/translate/vmx-impl.inc.c:835:
+^I^Ivdivsd, PPC_NONE, PPC2_ISA300, 0x00000000);$

WARNING: line over 80 characters
#123: FILE: target/ppc/translate/vmx-ops.inc.c:54:
+#define GEN_VXFORM_DUAL_BOTH(name0, name1, opc2, opc3, inval0, inval1, type0, type1) \

ERROR: code indent should never use tabs
#136: FILE: target/ppc/translate/vmx-ops.inc.c:122:
+^I^I^IPPC_ALTIVEC, PPC2_ISA300),$

ERROR: code indent should never use tabs
#138: FILE: target/ppc/translate/vmx-ops.inc.c:124:
+^I^I^IPPC_ALTIVEC, PPC2_ISA300),$

total: 4 errors, 1 warnings, 108 lines checked

Patch 6/6 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200613042029.22321-1-ljp@linux.ibm.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
David Gibson June 15, 2020, 8:49 a.m. UTC | #2 
On Fri, Jun 12, 2020 at 09:47:58PM -0700, no-reply@patchew.org wrote:
> Patchew URL:
> https://patchew.org/QEMU/20200613042029.22321-1-ljp@linux.ibm.com/

I will need you to fix these stype errors and repost.

> 
> 
> 
> Hi,
> 
> This series seems to have some coding style problems. See output below for
> more information:
> 
> Message-id: 20200613042029.22321-1-ljp@linux.ibm.com
> Subject: [PATCH 0/6] Add several Power ISA 3.1 32/64-bit vector instructions
> Type: series
> 
> === TEST SCRIPT BEGIN ===
> #!/bin/bash
> git rev-parse base > /dev/null || exit 0
> git config --local diff.renamelimit 0
> git config --local diff.renames True
> git config --local diff.algorithm histogram
> ./scripts/checkpatch.pl --mailback base..
> === TEST SCRIPT END ===
> 
> Switched to a new branch 'test'
> d39f30e target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions
> 966b641 fix the prototype of muls64/mulu64
> 42111c5 target/ppc: add vmulh{su}d instructions
> c96e996 targetc/ppc: add vmulh{su}w instructions
> c52004c target/ppc: add vmulld instruction
> 1061e4e target/ppc: add byte-reverse br[dwh] instructions
> 
> === OUTPUT BEGIN ===
> 1/6 Checking commit 1061e4ead5bc (target/ppc: add byte-reverse br[dwh] instructions)
> ERROR: code indent should never use tabs
> #26: FILE: target/ppc/translate.c:6977:
> +^ITCGv_i64 temp = tcg_temp_new_i64();$
> 
> ERROR: code indent should never use tabs
> #28: FILE: target/ppc/translate.c:6979:
> +^Itcg_gen_bswap64_i64(temp, cpu_gpr[rS(ctx->opcode)]);$
> 
> WARNING: line over 80 characters
> #29: FILE: target/ppc/translate.c:6980:
> +       tcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)]));
> 
> ERROR: code indent should never use tabs
> #29: FILE: target/ppc/translate.c:6980:
> +^Itcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)]));$
> 
> ERROR: code indent should never use tabs
> #31: FILE: target/ppc/translate.c:6982:
> +^Itcg_temp_free_i64(temp);$
> 
> ERROR: code indent should never use tabs
> #37: FILE: target/ppc/translate.c:6988:
> +^ITCGv_i64 temp = tcg_temp_new_i64();$
> 
> ERROR: code indent should never use tabs
> #38: FILE: target/ppc/translate.c:6989:
> +^ITCGv_i64 lsb = tcg_temp_new_i64();$
> 
> ERROR: code indent should never use tabs
> #39: FILE: target/ppc/translate.c:6990:
> +^ITCGv_i64 msb = tcg_temp_new_i64();$
> 
> ERROR: code indent should never use tabs
> #41: FILE: target/ppc/translate.c:6992:
> +^Itcg_gen_movi_i64(lsb, 0x00000000ffffffffull);$
> 
> ERROR: code indent should never use tabs
> #42: FILE: target/ppc/translate.c:6993:
> +^Itcg_gen_and_i64(temp, lsb, cpu_gpr[rS(ctx->opcode)]);$
> 
> ERROR: code indent should never use tabs
> #43: FILE: target/ppc/translate.c:6994:
> +^Itcg_gen_bswap32_i64(lsb, temp);$
> 
> ERROR: trailing whitespace
> #44: FILE: target/ppc/translate.c:6995:
> +^I$
> 
> ERROR: code indent should never use tabs
> #44: FILE: target/ppc/translate.c:6995:
> +^I$
> 
> ERROR: code indent should never use tabs
> #45: FILE: target/ppc/translate.c:6996:
> +^Itcg_gen_shri_i64(msb, cpu_gpr[rS(ctx->opcode)], 32);$
> 
> ERROR: code indent should never use tabs
> #46: FILE: target/ppc/translate.c:6997:
> +^Itcg_gen_bswap32_i64(temp, msb);$
> 
> ERROR: code indent should never use tabs
> #47: FILE: target/ppc/translate.c:6998:
> +^Itcg_gen_shli_i64(msb, temp, 32);$
> 
> ERROR: trailing whitespace
> #48: FILE: target/ppc/translate.c:6999:
> +^I$
> 
> ERROR: code indent should never use tabs
> #48: FILE: target/ppc/translate.c:6999:
> +^I$
> 
> ERROR: code indent should never use tabs
> #49: FILE: target/ppc/translate.c:7000:
> +^Itcg_gen_or_i64(temp, lsb, msb);$
> 
> WARNING: line over 80 characters
> #51: FILE: target/ppc/translate.c:7002:
> +       tcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)]));
> 
> ERROR: code indent should never use tabs
> #51: FILE: target/ppc/translate.c:7002:
> +^Itcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)]));$
> 
> ERROR: code indent should never use tabs
> #53: FILE: target/ppc/translate.c:7004:
> +^Itcg_temp_free_i64(temp);$
> 
> ERROR: code indent should never use tabs
> #54: FILE: target/ppc/translate.c:7005:
> +^Itcg_temp_free_i64(lsb);$
> 
> ERROR: code indent should never use tabs
> #55: FILE: target/ppc/translate.c:7006:
> +^Itcg_temp_free_i64(msb);$
> 
> ERROR: code indent should never use tabs
> #61: FILE: target/ppc/translate.c:7012:
> +^ITCGv_i64 temp = tcg_temp_new_i64();$
> 
> ERROR: code indent should never use tabs
> #62: FILE: target/ppc/translate.c:7013:
> +^ITCGv_i64 t0 = tcg_temp_new_i64();$
> 
> ERROR: code indent should never use tabs
> #63: FILE: target/ppc/translate.c:7014:
> +^ITCGv_i64 t1 = tcg_temp_new_i64();$
> 
> ERROR: code indent should never use tabs
> #64: FILE: target/ppc/translate.c:7015:
> +^ITCGv_i64 t2 = tcg_temp_new_i64();$
> 
> ERROR: code indent should never use tabs
> #65: FILE: target/ppc/translate.c:7016:
> +^ITCGv_i64 t3 = tcg_temp_new_i64();$
> 
> ERROR: code indent should never use tabs
> #67: FILE: target/ppc/translate.c:7018:
> +^Itcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);$
> 
> ERROR: code indent should never use tabs
> #68: FILE: target/ppc/translate.c:7019:
> +^Itcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);$
> 
> ERROR: code indent should never use tabs
> #69: FILE: target/ppc/translate.c:7020:
> +^Itcg_gen_and_i64(t2, t1, t0);$
> 
> ERROR: code indent should never use tabs
> #70: FILE: target/ppc/translate.c:7021:
> +^Itcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0);$
> 
> ERROR: code indent should never use tabs
> #71: FILE: target/ppc/translate.c:7022:
> +^Itcg_gen_shli_i64(t1, t1, 8);$
> 
> ERROR: code indent should never use tabs
> #72: FILE: target/ppc/translate.c:7023:
> +^Itcg_gen_or_i64(temp, t1, t2);$
> 
> WARNING: line over 80 characters
> #73: FILE: target/ppc/translate.c:7024:
> +       tcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)]));
> 
> ERROR: code indent should never use tabs
> #73: FILE: target/ppc/translate.c:7024:
> +^Itcg_gen_st_i64(temp, cpu_env, offsetof(CPUPPCState, gpr[rA(ctx->opcode)]));$
> 
> ERROR: code indent should never use tabs
> #75: FILE: target/ppc/translate.c:7026:
> +^Itcg_temp_free_i64(temp);$
> 
> ERROR: code indent should never use tabs
> #76: FILE: target/ppc/translate.c:7027:
> +^Itcg_temp_free_i64(t0);$
> 
> ERROR: code indent should never use tabs
> #77: FILE: target/ppc/translate.c:7028:
> +^Itcg_temp_free_i64(t1);$
> 
> ERROR: code indent should never use tabs
> #78: FILE: target/ppc/translate.c:7029:
> +^Itcg_temp_free_i64(t2);$
> 
> ERROR: code indent should never use tabs
> #79: FILE: target/ppc/translate.c:7030:
> +^Itcg_temp_free_i64(t3);$
> 
> total: 39 errors, 3 warnings, 69 lines checked
> 
> Patch 1/6 has style problems, please review.  If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.
> 
> 2/6 Checking commit c52004cd8f89 (target/ppc: add vmulld instruction)
> 3/6 Checking commit c96e996917c6 (targetc/ppc: add vmulh{su}w instructions)
> ERROR: code indent should never use tabs
> #34: FILE: target/ppc/int_helper.c:526:
> +#define VMULH_DO(name, op, element, cast_orig, cast_temp)^I^I\$
> 
> ERROR: code indent should never use tabs
> #35: FILE: target/ppc/int_helper.c:527:
> +    void helper_vmulh##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)^I\$
> 
> ERROR: code indent should never use tabs
> #36: FILE: target/ppc/int_helper.c:528:
> +    {^I^I^I^I^I^I^I^I^I\$
> 
> ERROR: code indent should never use tabs
> #37: FILE: target/ppc/int_helper.c:529:
> +^Iint i;^I^I^I^I^I^I^I^I\$
> 
> ERROR: code indent should never use tabs
> #38: FILE: target/ppc/int_helper.c:530:
> +^I^I^I^I^I^I^I^I^I\$
> 
> ERROR: code indent should never use tabs
> #39: FILE: target/ppc/int_helper.c:531:
> +^Ifor (i = 0; i < ARRAY_SIZE(r->element); i++) {^I^I^I\$
> 
> ERROR: code indent should never use tabs
> #40: FILE: target/ppc/int_helper.c:532:
> +^I^Ir->element[i] = (cast_orig)(((cast_temp)a->element[i] op \$
> 
> ERROR: code indent should never use tabs
> #41: FILE: target/ppc/int_helper.c:533:
> +^I^I^I^I(cast_temp)b->element[i]) >> 32);^I\$
> 
> ERROR: code indent should never use tabs
> #42: FILE: target/ppc/int_helper.c:534:
> +^I}^I^I^I^I^I^I^I^I\$
> 
> ERROR: code indent should never use tabs
> #61: FILE: target/ppc/translate/vmx-impl.inc.c:816:
> +^I^Ivmulhuw, PPC_NONE, PPC2_ISA300);$
> 
> ERROR: code indent should never use tabs
> #67: FILE: target/ppc/translate/vmx-impl.inc.c:822:
> +^I^Ivmulhsw, PPC_NONE, PPC2_ISA300);$
> 
> total: 11 errors, 0 warnings, 55 lines checked
> 
> Patch 3/6 has style problems, please review.  If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.
> 
> 4/6 Checking commit 42111c50379b (target/ppc: add vmulh{su}d instructions)
> ERROR: code indent should never use tabs
> #36: FILE: target/ppc/int_helper.c:528:
> +^Iint i;$
> 
> ERROR: code indent should never use tabs
> #37: FILE: target/ppc/int_helper.c:529:
> +^Iuint64_t h64 = 0;$
> 
> ERROR: code indent should never use tabs
> #38: FILE: target/ppc/int_helper.c:530:
> +^Iuint64_t l64 = 0;$
> 
> ERROR: code indent should never use tabs
> #40: FILE: target/ppc/int_helper.c:532:
> +^Ifor (i = 0; i < 2; i++) {$
> 
> ERROR: code indent should never use tabs
> #41: FILE: target/ppc/int_helper.c:533:
> +^I^Imuls64(&l64, &h64, a->s64[i], b->s64[i]);$
> 
> ERROR: code indent should never use tabs
> #42: FILE: target/ppc/int_helper.c:534:
> +^I^Ir->s64[i] = h64;$
> 
> ERROR: code indent should never use tabs
> #43: FILE: target/ppc/int_helper.c:535:
> +^I}$
> 
> ERROR: code indent should never use tabs
> #48: FILE: target/ppc/int_helper.c:540:
> +^Iint i;$
> 
> ERROR: code indent should never use tabs
> #49: FILE: target/ppc/int_helper.c:541:
> +^Iuint64_t h64 = 0;$
> 
> ERROR: code indent should never use tabs
> #50: FILE: target/ppc/int_helper.c:542:
> +^Iuint64_t l64 = 0;$
> 
> ERROR: code indent should never use tabs
> #52: FILE: target/ppc/int_helper.c:544:
> +^Ifor (i = 0; i < 2; i++) {$
> 
> ERROR: code indent should never use tabs
> #53: FILE: target/ppc/int_helper.c:545:
> +^I^Imulu64(&l64, &h64, a->s64[i], b->s64[i]);$
> 
> ERROR: code indent should never use tabs
> #54: FILE: target/ppc/int_helper.c:546:
> +^I^Ir->u64[i] = h64;$
> 
> ERROR: code indent should never use tabs
> #55: FILE: target/ppc/int_helper.c:547:
> +^I}$
> 
> total: 14 errors, 0 warnings, 63 lines checked
> 
> Patch 4/6 has style problems, please review.  If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.
> 
> 5/6 Checking commit 966b641eba85 (fix the prototype of muls64/mulu64)
> 6/6 Checking commit d39f30e2a46f (target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions)
> ERROR: code indent should never use tabs
> #104: FILE: target/ppc/translate/vmx-impl.inc.c:832:
> +^I^Ivdivsw, PPC_NONE, PPC2_ISA300, 0x00000000);$
> 
> ERROR: code indent should never use tabs
> #107: FILE: target/ppc/translate/vmx-impl.inc.c:835:
> +^I^Ivdivsd, PPC_NONE, PPC2_ISA300, 0x00000000);$
> 
> WARNING: line over 80 characters
> #123: FILE: target/ppc/translate/vmx-ops.inc.c:54:
> +#define GEN_VXFORM_DUAL_BOTH(name0, name1, opc2, opc3, inval0, inval1, type0, type1) \
> 
> ERROR: code indent should never use tabs
> #136: FILE: target/ppc/translate/vmx-ops.inc.c:122:
> +^I^I^IPPC_ALTIVEC, PPC2_ISA300),$
> 
> ERROR: code indent should never use tabs
> #138: FILE: target/ppc/translate/vmx-ops.inc.c:124:
> +^I^I^IPPC_ALTIVEC, PPC2_ISA300),$
> 
> total: 4 errors, 1 warnings, 108 lines checked
> 
> Patch 6/6 has style problems, please review.  If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.
> 
> === OUTPUT END ===
> 
> Test command exited with code: 1
> 
> 
> The full log is available at
> http://patchew.org/logs/20200613042029.22321-1-ljp@linux.ibm.com/testing.checkpatch/?type=message.
> ---
> Email generated automatically by Patchew [https://patchew.org/].
> Please send your feedback to patchew-devel@redhat.com
Cédric Le Goater June 15, 2020, 5:36 p.m. UTC | #3 
Hello,

On 6/13/20 6:20 AM, Lijun Pan wrote:
> This patch series add several newly introduced 32/64-bit vector
> instructions in Power ISA 3.1. The newly added instructions are
> flagged as ISA300 temporarily in vmx-ops.inc.c and vmx-impl.inc.c
> to make them compile and function since Power ISA 3.1, together
> with next generation processor, has not been fully enabled in QEMU
> yet. When Power ISA 3.1 and next generation processor are fully
> supported, the flags should be changed.

What do you mean ? 

ISA 3.1 and POWER10 are merged in Linux and in the QEMU pseries 
and PowerNV (OPAL) machines.

It's very much empty but it's there.

C. 


> 
> Lijun Pan (6):
>   target/ppc: add byte-reverse br[dwh] instructions
>   target/ppc: add vmulld instruction
>   targetc/ppc: add vmulh{su}w instructions
>   target/ppc: add vmulh{su}d instructions
>   fix the prototype of muls64/mulu64
>   target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions
> 
>  include/qemu/host-utils.h           |  4 +-
>  target/ppc/helper.h                 | 13 ++++++
>  target/ppc/int_helper.c             | 58 +++++++++++++++++++++++++
>  target/ppc/translate.c              | 65 +++++++++++++++++++++++++++++
>  target/ppc/translate/vmx-impl.inc.c | 24 +++++++++++
>  target/ppc/translate/vmx-ops.inc.c  | 22 ++++++++--
>  6 files changed, 180 insertions(+), 6 deletions(-)
>
Lijun Pan June 15, 2020, 8:54 p.m. UTC | #4 
> On Jun 15, 2020, at 12:36 PM, Cédric Le Goater <clg@kaod.org> wrote:
> 
> Hello,
> 
> On 6/13/20 6:20 AM, Lijun Pan wrote:
>> This patch series add several newly introduced 32/64-bit vector
>> instructions in Power ISA 3.1. The newly added instructions are
>> flagged as ISA300 temporarily in vmx-ops.inc.c and vmx-impl.inc.c
>> to make them compile and function since Power ISA 3.1, together
>> with next generation processor, has not been fully enabled in QEMU
>> yet. When Power ISA 3.1 and next generation processor are fully
>> supported, the flags should be changed.
> 
> What do you mean ? 
> 
> ISA 3.1 and POWER10 are merged in Linux and in the QEMU pseries 
> and PowerNV (OPAL) machines.
> 
> It's very much empty but it's there.

I mean it does not work if you boots the guest in TCG mode, not KVM mode.

Lijun

> 
> C. 
> 
> 
>> 
>> Lijun Pan (6):
>>  target/ppc: add byte-reverse br[dwh] instructions
>>  target/ppc: add vmulld instruction
>>  targetc/ppc: add vmulh{su}w instructions
>>  target/ppc: add vmulh{su}d instructions
>>  fix the prototype of muls64/mulu64
>>  target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions
>> 
>> include/qemu/host-utils.h           |  4 +-
>> target/ppc/helper.h                 | 13 ++++++
>> target/ppc/int_helper.c             | 58 +++++++++++++++++++++++++
>> target/ppc/translate.c              | 65 +++++++++++++++++++++++++++++
>> target/ppc/translate/vmx-impl.inc.c | 24 +++++++++++
>> target/ppc/translate/vmx-ops.inc.c  | 22 ++++++++--
>> 6 files changed, 180 insertions(+), 6 deletions(-)
>> 
>
Cédric Le Goater June 16, 2020, 6 a.m. UTC | #5 
On 6/15/20 10:54 PM, Lijun Pan wrote:
> 
> 
>> On Jun 15, 2020, at 12:36 PM, Cédric Le Goater <clg@kaod.org> wrote:
>>
>> Hello,
>>
>> On 6/13/20 6:20 AM, Lijun Pan wrote:
>>> This patch series add several newly introduced 32/64-bit vector
>>> instructions in Power ISA 3.1. The newly added instructions are
>>> flagged as ISA300 temporarily in vmx-ops.inc.c and vmx-impl.inc.c
>>> to make them compile and function since Power ISA 3.1, together
>>> with next generation processor, has not been fully enabled in QEMU
>>> yet. When Power ISA 3.1 and next generation processor are fully
>>> supported, the flags should be changed.
>>
>> What do you mean ? 
>>
>> ISA 3.1 and POWER10 are merged in Linux and in the QEMU pseries 
>> and PowerNV (OPAL) machines.
>>
>> It's very much empty but it's there.
> 
> I mean it does not work if you boots the guest in TCG mode, not KVM mode.

Something is wrong in your environment. With the latest QEMU and
Linux 5.8-rc1, here is a POWER10 pseries machine : 
    
    BusyBox v1.30.1 (Ubuntu 1:1.30.1-4ubuntu4) built-in shell (ash)
    Enter 'help' for a list of built-in commands.
    
    (initramfs) 
    (initramfs) cat /proc/cpuinfo 
    processor	: 0
    cpu		: POWER10 (architected), altivec supported
    clock	: 1000.000000MHz
    revision	: 1.0 (pvr 0080 0100)
    
    processor	: 1
    cpu		: POWER10 (architected), altivec supported
    clock	: 1000.000000MHz
    revision	: 1.0 (pvr 0080 0100)
    
    processor	: 2
    cpu		: POWER10 (architected), altivec supported
    clock	: 1000.000000MHz
    revision	: 1.0 (pvr 0080 0100)
    
    processor	: 3
    cpu		: POWER10 (architected), altivec supported
    clock	: 1000.000000MHz
    revision	: 1.0 (pvr 0080 0100)
    
    timebase	: 512000000
    platform	: pSeries
    model	: IBM pSeries (emulated by qemu)
    machine	: CHRP IBM pSeries (emulated by qemu)
    MMU		: Radix
    (initramfs) uname -a 
    Linux (none) 5.8.0-rc1+ #199 SMP Tue Jun 16 07:54:06 CEST 2020 ppc64le GNU/Linux



KVM works also but you will need to run the guest under a QEMU
PowerNV machine using my powernv-5.1 branch. All support for
POWER10 baremetal is not merged yet.

Thanks,

C.
Richard Henderson June 18, 2020, 11:51 p.m. UTC | #6 
On 6/12/20 9:20 PM, Lijun Pan wrote:
> This patch series add several newly introduced 32/64-bit vector
> instructions in Power ISA 3.1. The newly added instructions are
> flagged as ISA300 temporarily in vmx-ops.inc.c and vmx-impl.inc.c
> to make them compile and function since Power ISA 3.1, together
> with next generation processor, has not been fully enabled in QEMU
> yet. When Power ISA 3.1 and next generation processor are fully
> supported, the flags should be changed.

This is not the correct procedure.

Step 1 is to add a new define for ISA301, which is not enabled for any processor.

Step 2 is to add all of the new instructions, using ISA301.  In this way there
is no intermediate point in which a 3.01 instruction is enabled for 3.00.  In
addition, we do not have extra churn simply to change the ISA.

Step 3 is to add a new processor for which ISA301 is set.  It is often
reasonable to have a fake processor named "max" that contains all of the
available features.  For ppc, I see that "max" is currently aliased to "7400_v2.9".


r~