| Message ID | 1590680799-5640-1-git-send-email-tharvey@gateworks.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | e8510d43f219beff1f426080049a5462148afd2f |
| Headers | show |
| Series | [RFC] spi: spi-cavium-thunderx: flag controller as half duplex | expand |
On Thu, 28 May 2020 08:46:39 -0700, Tim Harvey wrote: > The OcteonTX (TX1/ThunderX) SPI controller does not support full > duplex transactions. Set the appropriate flag such that the spi > core will return -EINVAL on such transactions requested by chip > drivers. > > This is an RFC as I need someone from Marvell/Cavium to confirm > if this driver is used for other silicon that does support > full duplex transfers (in which case we will need to identify > that we are running on the ThunderX arch before setting the flag). Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/1] spi: spi-cavium-thunderx: flag controller as half duplex commit: e8510d43f219beff1f426080049a5462148afd2f All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
diff --git a/drivers/spi/spi-cavium-thunderx.c b/drivers/spi/spi-cavium-thunderx.c index fd6b9ca..60c0d69 100644 --- a/drivers/spi/spi-cavium-thunderx.c +++ b/drivers/spi/spi-cavium-thunderx.c @@ -64,6 +64,7 @@ static int thunderx_spi_probe(struct pci_dev *pdev, p->sys_freq = SYS_FREQ_DEFAULT; dev_info(dev, "Set system clock to %u\n", p->sys_freq); + master->flags = SPI_MASTER_HALF_DUPLEX; master->num_chipselect = 4; master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | SPI_3WIRE;
The OcteonTX (TX1/ThunderX) SPI controller does not support full duplex transactions. Set the appropriate flag such that the spi core will return -EINVAL on such transactions requested by chip drivers. This is an RFC as I need someone from Marvell/Cavium to confirm if this driver is used for other silicon that does support full duplex transfers (in which case we will need to identify that we are running on the ThunderX arch before setting the flag). Cc: Robert Richter <rrichter@marvell.com> Signed-off-by: Tim Harvey <tharvey@gateworks.com> --- drivers/spi/spi-cavium-thunderx.c | 1 + 1 file changed, 1 insertion(+)