| Message ID | 20200617030029.4082-4-chao.hao@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MT6779 IOMMU SUPPORT | expand |
On 17/06/2020 05:00, Chao Hao wrote: > Add F_MMU_IN_ORDER_WR_EN definition in MISC_CTRL. > In order to improve performance, we always disable STANDARD_AXI_MODE > and IN_ORDER_WR_EN in MISC_CTRL. > > Change since v3: The changelog should go below the '---' as we don't want this in the git history once the patch get's accepted. > 1. Rename Disable STANDARD_AXI_MODE in MISC_CTRL to Set MISC_CTRL register > 2. Add F_MMU_IN_DRDER_WR_EN definition in MISC_CTRL > We need to disable in_order_write to improve performance > > Cc: Yong Wu <yong.wu@mediatek.com> > Signed-off-by: Chao Hao <chao.hao@mediatek.com> > --- > drivers/iommu/mtk_iommu.c | 11 +++++++++++ > drivers/iommu/mtk_iommu.h | 1 + > 2 files changed, 12 insertions(+) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 88d3df5b91c2..239d2cdbbc9f 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -42,6 +42,9 @@ > #define F_INVLD_EN1 BIT(1) > > #define REG_MMU_MISC_CTRL 0x048 > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) > + > #define REG_MMU_DCM_DIS 0x050 > > #define REG_MMU_CTRL_REG 0x110 > @@ -578,6 +581,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > } > > + if (data->plat_data->has_misc_ctrl) { That's confusing. We renamed the register to misc_ctrl, but it's present in all SoCs. We should find a better name for this flag to describe what the hardware supports. Regards, Matthias > + /* For mm_iommu, it can improve performance by the setting */ > + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); > + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > + regval &= ~F_MMU_IN_ORDER_WR_EN; > + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > + } > + > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > dev_name(data->dev), (void *)data)) { > writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > index 1b6ea839b92c..d711ac630037 100644 > --- a/drivers/iommu/mtk_iommu.h > +++ b/drivers/iommu/mtk_iommu.h > @@ -40,6 +40,7 @@ struct mtk_iommu_plat_data { > > /* HW will use the EMI clock if there isn't the "bclk". */ > bool has_bclk; > + bool has_misc_ctrl; > bool has_vld_pa_rng; > bool reset_axi; > unsigned char larbid_remap[MTK_LARB_NR_MAX]; >
On Wed, 2020-06-17 at 11:34 +0200, Matthias Brugger wrote: > > On 17/06/2020 05:00, Chao Hao wrote: > > Add F_MMU_IN_ORDER_WR_EN definition in MISC_CTRL. > > In order to improve performance, we always disable STANDARD_AXI_MODE > > and IN_ORDER_WR_EN in MISC_CTRL. > > > > Change since v3: > > The changelog should go below the '---' as we don't want this in the git history > once the patch get's accepted. > okok, thanks > > 1. Rename Disable STANDARD_AXI_MODE in MISC_CTRL to Set MISC_CTRL register > > 2. Add F_MMU_IN_DRDER_WR_EN definition in MISC_CTRL > > We need to disable in_order_write to improve performance > > > > Cc: Yong Wu <yong.wu@mediatek.com> > > Signed-off-by: Chao Hao <chao.hao@mediatek.com> > > --- > > drivers/iommu/mtk_iommu.c | 11 +++++++++++ > > drivers/iommu/mtk_iommu.h | 1 + > > 2 files changed, 12 insertions(+) > > > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > > index 88d3df5b91c2..239d2cdbbc9f 100644 > > --- a/drivers/iommu/mtk_iommu.c > > +++ b/drivers/iommu/mtk_iommu.c > > @@ -42,6 +42,9 @@ > > #define F_INVLD_EN1 BIT(1) > > > > #define REG_MMU_MISC_CTRL 0x048 > > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > > +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) > > + > > #define REG_MMU_DCM_DIS 0x050 > > > > #define REG_MMU_CTRL_REG 0x110 > > @@ -578,6 +581,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > > writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > > } > > > > + if (data->plat_data->has_misc_ctrl) { > > That's confusing. We renamed the register to misc_ctrl, but it's present in all > SoCs. We should find a better name for this flag to describe what the hardware > supports. > ok, thanks for you advice, I will rename it in next version. ex:has_perf_req(has performance requirement) > Regards, > Matthias > > > + /* For mm_iommu, it can improve performance by the setting */ > > + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); > > + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > > + regval &= ~F_MMU_IN_ORDER_WR_EN; > > + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > > + } > > + > > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > > dev_name(data->dev), (void *)data)) { > > writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); > > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > > index 1b6ea839b92c..d711ac630037 100644 > > --- a/drivers/iommu/mtk_iommu.h > > +++ b/drivers/iommu/mtk_iommu.h > > @@ -40,6 +40,7 @@ struct mtk_iommu_plat_data { > > > > /* HW will use the EMI clock if there isn't the "bclk". */ > > bool has_bclk; > > + bool has_misc_ctrl; > > bool has_vld_pa_rng; > > bool reset_axi; > > unsigned char larbid_remap[MTK_LARB_NR_MAX]; > >
On Sat, 2020-06-20 at 10:03 +0800, Yong Wu wrote: > Hi Chao, > > On Thu, 2020-06-18 at 19:49 +0800, chao hao wrote: > > On Wed, 2020-06-17 at 11:34 +0200, Matthias Brugger wrote: > > [snip] > > > > > > > > > #define REG_MMU_MISC_CTRL 0x048 > > > > +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) > > > > +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) > > > > + > > > > #define REG_MMU_DCM_DIS 0x050 > > > > > > > > #define REG_MMU_CTRL_REG 0x110 > > > > @@ -578,6 +581,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > > > > writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > > > > } > > > > > > > > + if (data->plat_data->has_misc_ctrl) { > > > > > > That's confusing. We renamed the register to misc_ctrl, but it's present in all > > > SoCs. We should find a better name for this flag to describe what the hardware > > > supports. > > > > > > > ok, thanks for you advice, I will rename it in next version. > > ex:has_perf_req(has performance requirement) > > > > > > > Regards, > > > Matthias > > > > > > > + /* For mm_iommu, it can improve performance by the setting */ > > > > + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); > > > > + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > > > > + regval &= ~F_MMU_IN_ORDER_WR_EN; > > Note: mt2712 also is MISC_CTRL register, but it don't use this > in_order setting. > > As commented in v3. 0x48 is either STANDARD_AXI_MODE or MISC_CTRL > register. No need two flags(reset_axi/has_xx) for it. > > something like: > > regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); > if (reset_axi) { > regval = 0; > } else { /* MISC_CTRL */ > if (!apu[1]) > regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; > if (out_order_en) > regval &= ~F_MMU_IN_ORDER_WR_EN; > } > writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > > > [1] Your current patch doesn't support apu-iommu, thus, add it when > necessary. ok, the patchset don't need to "if (!apu[1])", I will fix it in next version. thanks > > > > + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); > > > > + } > > > > + > > > > if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, > > > > dev_name(data->dev), (void *)data)) { > > > > writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); > > > > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > > > > index 1b6ea839b92c..d711ac630037 100644 > > > > --- a/drivers/iommu/mtk_iommu.h > > > > +++ b/drivers/iommu/mtk_iommu.h > > > > @@ -40,6 +40,7 @@ struct mtk_iommu_plat_data { > > > > > > > > /* HW will use the EMI clock if there isn't the "bclk". */ > > > > bool has_bclk; > > > > + bool has_misc_ctrl; > > > > bool has_vld_pa_rng; > > > > bool reset_axi; > > > > unsigned char larbid_remap[MTK_LARB_NR_MAX]; > > > > > > > > >
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 88d3df5b91c2..239d2cdbbc9f 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -42,6 +42,9 @@ #define F_INVLD_EN1 BIT(1) #define REG_MMU_MISC_CTRL 0x048 +#define F_MMU_IN_ORDER_WR_EN (BIT(1) | BIT(17)) +#define F_MMU_STANDARD_AXI_MODE_BIT (BIT(3) | BIT(19)) + #define REG_MMU_DCM_DIS 0x050 #define REG_MMU_CTRL_REG 0x110 @@ -578,6 +581,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); } + if (data->plat_data->has_misc_ctrl) { + /* For mm_iommu, it can improve performance by the setting */ + regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); + regval &= ~F_MMU_STANDARD_AXI_MODE_BIT; + regval &= ~F_MMU_IN_ORDER_WR_EN; + writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); + } + if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, dev_name(data->dev), (void *)data)) { writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 1b6ea839b92c..d711ac630037 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -40,6 +40,7 @@ struct mtk_iommu_plat_data { /* HW will use the EMI clock if there isn't the "bclk". */ bool has_bclk; + bool has_misc_ctrl; bool has_vld_pa_rng; bool reset_axi; unsigned char larbid_remap[MTK_LARB_NR_MAX];
Add F_MMU_IN_ORDER_WR_EN definition in MISC_CTRL. In order to improve performance, we always disable STANDARD_AXI_MODE and IN_ORDER_WR_EN in MISC_CTRL. Change since v3: 1. Rename Disable STANDARD_AXI_MODE in MISC_CTRL to Set MISC_CTRL register 2. Add F_MMU_IN_DRDER_WR_EN definition in MISC_CTRL We need to disable in_order_write to improve performance Cc: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Chao Hao <chao.hao@mediatek.com> --- drivers/iommu/mtk_iommu.c | 11 +++++++++++ drivers/iommu/mtk_iommu.h | 1 + 2 files changed, 12 insertions(+)