| Message ID | 20200617123844.29960-2-steven.price@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MTE support for KVM guest | expand |
On Wed, Jun 17, 2020 at 01:38:43PM +0100, Steven Price wrote: > diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c > index 75b1925763f1..6ecee1528566 100644 > --- a/arch/arm64/kvm/hyp/sysreg-sr.c > +++ b/arch/arm64/kvm/hyp/sysreg-sr.c > @@ -26,6 +26,12 @@ > static void __hyp_text __sysreg_save_common_state(struct kvm_cpu_context *ctxt) > { > ctxt->sys_regs[MDSCR_EL1] = read_sysreg(mdscr_el1); > + if (system_supports_mte()) { > + ctxt->sys_regs[RGSR_EL1] = read_sysreg_s(SYS_RGSR_EL1); > + ctxt->sys_regs[GCR_EL1] = read_sysreg_s(SYS_GCR_EL1); > + ctxt->sys_regs[TFSRE0_EL1] = read_sysreg_s(SYS_TFSRE0_EL1); > + ctxt->sys_regs[TFSR_EL1] = read_sysreg_s(SYS_TFSR_EL1); > + } TFSR_EL1 is not a common register as we have the TFSR_EL2 as well. So you'd have to access it as read_sysreg_el1(SYS_TFSR) so that, in the VHE case, it generates TFSR_EL12, otherwise you just save the host register. Also, since TFSR*_EL1 can be set asynchronously, I think we need to set the SCTLR_EL2.ITFSB bit so that the register update is synchronised on entry to EL2. With VHE we get this automatically as part of SCTLR_EL1_SET but it turns out that we have another SCTLR_ELx_FLAGS macro for the non-VHE case (why not calling this SCTLR_EL2_* I have no idea). > /* > * The host arm64 Linux uses sp_el0 to point to 'current' and it must > @@ -99,6 +105,12 @@ NOKPROBE_SYMBOL(sysreg_save_guest_state_vhe); > static void __hyp_text __sysreg_restore_common_state(struct kvm_cpu_context *ctxt) > { > write_sysreg(ctxt->sys_regs[MDSCR_EL1], mdscr_el1); > + if (system_supports_mte()) { > + write_sysreg_s(ctxt->sys_regs[RGSR_EL1], SYS_RGSR_EL1); > + write_sysreg_s(ctxt->sys_regs[GCR_EL1], SYS_GCR_EL1); > + write_sysreg_s(ctxt->sys_regs[TFSRE0_EL1], SYS_TFSRE0_EL1); > + write_sysreg_s(ctxt->sys_regs[TFSR_EL1], SYS_TFSR_EL1); > + } Similarly here, you override the TFSR_EL2 with VHE enabled.
On 17/06/2020 15:05, Catalin Marinas wrote: > On Wed, Jun 17, 2020 at 01:38:43PM +0100, Steven Price wrote: >> diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c >> index 75b1925763f1..6ecee1528566 100644 >> --- a/arch/arm64/kvm/hyp/sysreg-sr.c >> +++ b/arch/arm64/kvm/hyp/sysreg-sr.c >> @@ -26,6 +26,12 @@ >> static void __hyp_text __sysreg_save_common_state(struct kvm_cpu_context *ctxt) >> { >> ctxt->sys_regs[MDSCR_EL1] = read_sysreg(mdscr_el1); >> + if (system_supports_mte()) { >> + ctxt->sys_regs[RGSR_EL1] = read_sysreg_s(SYS_RGSR_EL1); >> + ctxt->sys_regs[GCR_EL1] = read_sysreg_s(SYS_GCR_EL1); >> + ctxt->sys_regs[TFSRE0_EL1] = read_sysreg_s(SYS_TFSRE0_EL1); >> + ctxt->sys_regs[TFSR_EL1] = read_sysreg_s(SYS_TFSR_EL1); >> + } > > TFSR_EL1 is not a common register as we have the TFSR_EL2 as well. So > you'd have to access it as read_sysreg_el1(SYS_TFSR) so that, in the VHE > case, it generates TFSR_EL12, otherwise you just save the host register. Ah, thanks for pointing that out - I'd got myself confused with the whole VHE _EL12 registers. I'd managed to miss that TFSR is banked. > Also, since TFSR*_EL1 can be set asynchronously, I think we need to set > the SCTLR_EL2.ITFSB bit so that the register update is synchronised on > entry to EL2. With VHE we get this automatically as part of > SCTLR_EL1_SET but it turns out that we have another SCTLR_ELx_FLAGS > macro for the non-VHE case (why not calling this SCTLR_EL2_* I have no > idea). I hadn't noticed that there was a different set for the non-VHE case which was missing ITFSB - I'll update that. Thanks, Steve >> /* >> * The host arm64 Linux uses sp_el0 to point to 'current' and it must >> @@ -99,6 +105,12 @@ NOKPROBE_SYMBOL(sysreg_save_guest_state_vhe); >> static void __hyp_text __sysreg_restore_common_state(struct kvm_cpu_context *ctxt) >> { >> write_sysreg(ctxt->sys_regs[MDSCR_EL1], mdscr_el1); >> + if (system_supports_mte()) { >> + write_sysreg_s(ctxt->sys_regs[RGSR_EL1], SYS_RGSR_EL1); >> + write_sysreg_s(ctxt->sys_regs[GCR_EL1], SYS_GCR_EL1); >> + write_sysreg_s(ctxt->sys_regs[TFSRE0_EL1], SYS_TFSRE0_EL1); >> + write_sysreg_s(ctxt->sys_regs[TFSR_EL1], SYS_TFSR_EL1); >> + } > > Similarly here, you override the TFSR_EL2 with VHE enabled. >
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 32c8a675e5a4..1f10e9dee2e0 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -92,6 +92,9 @@ struct kvm_arch { * supported. */ bool return_nisv_io_abort_to_user; + + /* If any VCPU has MTE enabled then all memory must be MTE enabled */ + bool vcpu_has_mte; }; #define KVM_NR_MEM_OBJS 40 @@ -123,6 +126,8 @@ enum vcpu_sysreg { SCTLR_EL1, /* System Control Register */ ACTLR_EL1, /* Auxiliary Control Register */ CPACR_EL1, /* Coprocessor Access Control */ + RGSR_EL1, /* Random Allocation Tag Seed Register */ + GCR_EL1, /* Tag Control Register */ ZCR_EL1, /* SVE Control */ TTBR0_EL1, /* Translation Table Base Register 0 */ TTBR1_EL1, /* Translation Table Base Register 1 */ @@ -139,6 +144,8 @@ enum vcpu_sysreg { TPIDR_EL1, /* Thread ID, Privileged */ AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ CNTKCTL_EL1, /* Timer Control Register (EL1) */ + TFSRE0_EL1, /* Tag Fault Status Register (EL0) */ + TFSR_EL1, /* Tag Fault Stauts Register (EL1) */ PAR_EL1, /* Physical Address Register */ MDSCR_EL1, /* Monitor Debug System Control Register */ MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c index 75b1925763f1..6ecee1528566 100644 --- a/arch/arm64/kvm/hyp/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/sysreg-sr.c @@ -26,6 +26,12 @@ static void __hyp_text __sysreg_save_common_state(struct kvm_cpu_context *ctxt) { ctxt->sys_regs[MDSCR_EL1] = read_sysreg(mdscr_el1); + if (system_supports_mte()) { + ctxt->sys_regs[RGSR_EL1] = read_sysreg_s(SYS_RGSR_EL1); + ctxt->sys_regs[GCR_EL1] = read_sysreg_s(SYS_GCR_EL1); + ctxt->sys_regs[TFSRE0_EL1] = read_sysreg_s(SYS_TFSRE0_EL1); + ctxt->sys_regs[TFSR_EL1] = read_sysreg_s(SYS_TFSR_EL1); + } /* * The host arm64 Linux uses sp_el0 to point to 'current' and it must @@ -99,6 +105,12 @@ NOKPROBE_SYMBOL(sysreg_save_guest_state_vhe); static void __hyp_text __sysreg_restore_common_state(struct kvm_cpu_context *ctxt) { write_sysreg(ctxt->sys_regs[MDSCR_EL1], mdscr_el1); + if (system_supports_mte()) { + write_sysreg_s(ctxt->sys_regs[RGSR_EL1], SYS_RGSR_EL1); + write_sysreg_s(ctxt->sys_regs[GCR_EL1], SYS_GCR_EL1); + write_sysreg_s(ctxt->sys_regs[TFSRE0_EL1], SYS_TFSRE0_EL1); + write_sysreg_s(ctxt->sys_regs[TFSR_EL1], SYS_TFSR_EL1); + } /* * The host arm64 Linux uses sp_el0 to point to 'current' and it must diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 51db934702b6..3ae008a9b0bd 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1095,6 +1095,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, if (!vcpu_has_sve(vcpu)) val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT); + } else if (id == SYS_ID_AA64PFR1_EL1) { + val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT); } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) { val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) | (0xfUL << ID_AA64ISAR1_API_SHIFT) | @@ -1504,6 +1506,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, + { SYS_DESC(SYS_RGSR_EL1), trap_raz_wi, reset_unknown, RGSR_EL1 }, + { SYS_DESC(SYS_GCR_EL1), trap_raz_wi, reset_unknown, GCR_EL1 }, { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, @@ -1528,6 +1532,9 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, + { SYS_DESC(SYS_TFSR_EL1), trap_raz_wi, reset_unknown, TFSR_EL1 }, + { SYS_DESC(SYS_TFSRE0_EL1), trap_raz_wi, reset_unknown, TFSRE0_EL1 }, + { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
Define the new system registers that MTE introduces and context switch them. Also hide the MTE feature from the ID register as it isn't supported in a VM yet. Signed-off-by: Steven Price <steven.price@arm.com> --- arch/arm64/include/asm/kvm_host.h | 7 +++++++ arch/arm64/kvm/hyp/sysreg-sr.c | 12 ++++++++++++ arch/arm64/kvm/sys_regs.c | 7 +++++++ 3 files changed, 26 insertions(+)