| Message ID | 20200629071310.1557-4-chao.hao@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MT6779 IOMMU SUPPORT | expand |
On 29/06/2020 09:13, Chao Hao wrote: > Given the fact that we are adding more and more plat_data bool values, > it would make sense to use a u32 flags register and add the appropriate > macro definitions to set and check for a flag present. > No functional change. > > Suggested-by: Matthias Brugger <matthias.bgg@gmail.com> > Signed-off-by: Chao Hao <chao.hao@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/iommu/mtk_iommu.c | 23 ++++++++++++----------- > drivers/iommu/mtk_iommu.h | 16 ++++++++++------ > 2 files changed, 22 insertions(+), 17 deletions(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 88d3df5b91c2..8f81df6cbe51 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -563,7 +563,8 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > upper_32_bits(data->protect_base); > writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); > > - if (data->enable_4GB && data->plat_data->has_vld_pa_rng) { > + if (data->enable_4GB && > + MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { > /* > * If 4GB mode is enabled, the validate PA range is from > * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. > @@ -573,7 +574,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) > } > writel_relaxed(0, data->base + REG_MMU_DCM_DIS); > > - if (data->plat_data->reset_axi) { > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { > /* The register is called STANDARD_AXI_MODE in this case */ > writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); > } > @@ -618,7 +619,7 @@ static int mtk_iommu_probe(struct platform_device *pdev) > > /* Whether the current dram is over 4GB */ > data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT)); > - if (!data->plat_data->has_4gb_mode) > + if (!MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) > data->enable_4GB = false; > > res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > @@ -631,7 +632,7 @@ static int mtk_iommu_probe(struct platform_device *pdev) > if (data->irq < 0) > return data->irq; > > - if (data->plat_data->has_bclk) { > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { > data->bclk = devm_clk_get(dev, "bclk"); > if (IS_ERR(data->bclk)) > return PTR_ERR(data->bclk); > @@ -763,23 +764,23 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = { > > static const struct mtk_iommu_plat_data mt2712_data = { > .m4u_plat = M4U_MT2712, > - .has_4gb_mode = true, > - .has_bclk = true, > - .has_vld_pa_rng = true, > + .flags = HAS_4GB_MODE | > + HAS_BCLK | > + HAS_VLD_PA_RNG, > .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, > }; > > static const struct mtk_iommu_plat_data mt8173_data = { > .m4u_plat = M4U_MT8173, > - .has_4gb_mode = true, > - .has_bclk = true, > - .reset_axi = true, > + .flags = HAS_4GB_MODE | > + HAS_BCLK | > + RESET_AXI, > .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ > }; > > static const struct mtk_iommu_plat_data mt8183_data = { > .m4u_plat = M4U_MT8183, > - .reset_axi = true, > + .flags = RESET_AXI, > .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1}, > }; > > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > index 1b6ea839b92c..7cc39f729263 100644 > --- a/drivers/iommu/mtk_iommu.h > +++ b/drivers/iommu/mtk_iommu.h > @@ -17,6 +17,15 @@ > #include <linux/spinlock.h> > #include <soc/mediatek/smi.h> > > +#define HAS_4GB_MODE BIT(0) > +/* HW will use the EMI clock if there isn't the "bclk". */ > +#define HAS_BCLK BIT(1) > +#define HAS_VLD_PA_RNG BIT(2) > +#define RESET_AXI BIT(3) > + > +#define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > + ((((pdata)->flags) & (_x)) == (_x)) > + > struct mtk_iommu_suspend_reg { > u32 misc_ctrl; > u32 dcm_dis; > @@ -36,12 +45,7 @@ enum mtk_iommu_plat { > > struct mtk_iommu_plat_data { > enum mtk_iommu_plat m4u_plat; > - bool has_4gb_mode; > - > - /* HW will use the EMI clock if there isn't the "bclk". */ > - bool has_bclk; > - bool has_vld_pa_rng; > - bool reset_axi; > + u32 flags; > unsigned char larbid_remap[MTK_LARB_NR_MAX]; > }; > >
Hi Chao, This is also ok for me. Only two format nitpick. On Mon, 2020-06-29 at 15:13 +0800, Chao Hao wrote: > Given the fact that we are adding more and more plat_data bool values, > it would make sense to use a u32 flags register and add the appropriate > macro definitions to set and check for a flag present. > No functional change. > > Suggested-by: Matthias Brugger <matthias.bgg@gmail.com> > Signed-off-by: Chao Hao <chao.hao@mediatek.com> > --- [snip] > static const struct mtk_iommu_plat_data mt2712_data = { > .m4u_plat = M4U_MT2712, > - .has_4gb_mode = true, > - .has_bclk = true, > - .has_vld_pa_rng = true, > + .flags = HAS_4GB_MODE | > + HAS_BCLK | > + HAS_VLD_PA_RNG, short enough. we can put it in one line? > .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, > }; > > static const struct mtk_iommu_plat_data mt8173_data = { > .m4u_plat = M4U_MT8173, > - .has_4gb_mode = true, > - .has_bclk = true, > - .reset_axi = true, > + .flags = HAS_4GB_MODE | > + HAS_BCLK | > + RESET_AXI, > .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ > }; > > static const struct mtk_iommu_plat_data mt8183_data = { > .m4u_plat = M4U_MT8183, > - .reset_axi = true, > + .flags = RESET_AXI, > .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1}, > }; > > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > index 1b6ea839b92c..7cc39f729263 100644 > --- a/drivers/iommu/mtk_iommu.h > +++ b/drivers/iommu/mtk_iommu.h > @@ -17,6 +17,15 @@ > #include <linux/spinlock.h> > #include <soc/mediatek/smi.h> > > +#define HAS_4GB_MODE BIT(0) > +/* HW will use the EMI clock if there isn't the "bclk". */ > +#define HAS_BCLK BIT(1) > +#define HAS_VLD_PA_RNG BIT(2) > +#define RESET_AXI BIT(3) > + > +#define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > + ((((pdata)->flags) & (_x)) == (_x)) If these definitions are not used in mtk_iommu_v1.c(also no this plan), then we can put them in the mtk_iommu.c. BTW, the patch title "modify the usage of mtk_iommu_plat_data structure" isn't so clear, we could write what the detailed modification is. something like: iommu/mediatek: Use a u32 flags to describe different HW features > + > struct mtk_iommu_suspend_reg { > u32 misc_ctrl; > u32 dcm_dis; > @@ -36,12 +45,7 @@ enum mtk_iommu_plat { > > struct mtk_iommu_plat_data { > enum mtk_iommu_plat m4u_plat; > - bool has_4gb_mode; > - > - /* HW will use the EMI clock if there isn't the "bclk". */ > - bool has_bclk; > - bool has_vld_pa_rng; > - bool reset_axi; > + u32 flags; > unsigned char larbid_remap[MTK_LARB_NR_MAX]; > }; >
On Tue, 2020-06-30 at 18:56 +0800, Yong Wu wrote: > Hi Chao, > > This is also ok for me. Only two format nitpick. > > On Mon, 2020-06-29 at 15:13 +0800, Chao Hao wrote: > > Given the fact that we are adding more and more plat_data bool values, > > it would make sense to use a u32 flags register and add the appropriate > > macro definitions to set and check for a flag present. > > No functional change. > > > > Suggested-by: Matthias Brugger <matthias.bgg@gmail.com> > > Signed-off-by: Chao Hao <chao.hao@mediatek.com> > > --- > > [snip] > > > static const struct mtk_iommu_plat_data mt2712_data = { > > .m4u_plat = M4U_MT2712, > > - .has_4gb_mode = true, > > - .has_bclk = true, > > - .has_vld_pa_rng = true, > > + .flags = HAS_4GB_MODE | > > + HAS_BCLK | > > + HAS_VLD_PA_RNG, > > short enough. we can put it in one line? ok, I will try to put it in one line in next version, thanks > > > .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, > > }; > > > > static const struct mtk_iommu_plat_data mt8173_data = { > > .m4u_plat = M4U_MT8173, > > - .has_4gb_mode = true, > > - .has_bclk = true, > > - .reset_axi = true, > > + .flags = HAS_4GB_MODE | > > + HAS_BCLK | > > + RESET_AXI, > > .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ > > }; > > > > static const struct mtk_iommu_plat_data mt8183_data = { > > .m4u_plat = M4U_MT8183, > > - .reset_axi = true, > > + .flags = RESET_AXI, > > .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1}, > > }; > > > > diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h > > index 1b6ea839b92c..7cc39f729263 100644 > > --- a/drivers/iommu/mtk_iommu.h > > +++ b/drivers/iommu/mtk_iommu.h > > @@ -17,6 +17,15 @@ > > #include <linux/spinlock.h> > > #include <soc/mediatek/smi.h> > > > > +#define HAS_4GB_MODE BIT(0) > > +/* HW will use the EMI clock if there isn't the "bclk". */ > > +#define HAS_BCLK BIT(1) > > +#define HAS_VLD_PA_RNG BIT(2) > > +#define RESET_AXI BIT(3) > > + > > +#define MTK_IOMMU_HAS_FLAG(pdata, _x) \ > > + ((((pdata)->flags) & (_x)) == (_x)) > > If these definitions are not used in mtk_iommu_v1.c(also no this plan), > then we can put them in the mtk_iommu.c. > ok, mtk_iommu_v1.c doesn't use these definitions. I will move them to mtk_iommu.c in next version, thanks. > > BTW, the patch title "modify the usage of mtk_iommu_plat_data structure" > isn't so clear, we could write what the detailed modification is. > something like: > iommu/mediatek: Use a u32 flags to describe different HW features > got it , thanks for you advice. > > + > > struct mtk_iommu_suspend_reg { > > u32 misc_ctrl; > > u32 dcm_dis; > > @@ -36,12 +45,7 @@ enum mtk_iommu_plat { > > > > struct mtk_iommu_plat_data { > > enum mtk_iommu_plat m4u_plat; > > - bool has_4gb_mode; > > - > > - /* HW will use the EMI clock if there isn't the "bclk". */ > > - bool has_bclk; > > - bool has_vld_pa_rng; > > - bool reset_axi; > > + u32 flags; > > unsigned char larbid_remap[MTK_LARB_NR_MAX]; > > }; > > > >
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 88d3df5b91c2..8f81df6cbe51 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -563,7 +563,8 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) upper_32_bits(data->protect_base); writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); - if (data->enable_4GB && data->plat_data->has_vld_pa_rng) { + if (data->enable_4GB && + MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { /* * If 4GB mode is enabled, the validate PA range is from * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30]. @@ -573,7 +574,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) } writel_relaxed(0, data->base + REG_MMU_DCM_DIS); - if (data->plat_data->reset_axi) { + if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { /* The register is called STANDARD_AXI_MODE in this case */ writel_relaxed(0, data->base + REG_MMU_MISC_CTRL); } @@ -618,7 +619,7 @@ static int mtk_iommu_probe(struct platform_device *pdev) /* Whether the current dram is over 4GB */ data->enable_4GB = !!(max_pfn > (BIT_ULL(32) >> PAGE_SHIFT)); - if (!data->plat_data->has_4gb_mode) + if (!MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) data->enable_4GB = false; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -631,7 +632,7 @@ static int mtk_iommu_probe(struct platform_device *pdev) if (data->irq < 0) return data->irq; - if (data->plat_data->has_bclk) { + if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { data->bclk = devm_clk_get(dev, "bclk"); if (IS_ERR(data->bclk)) return PTR_ERR(data->bclk); @@ -763,23 +764,23 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = { static const struct mtk_iommu_plat_data mt2712_data = { .m4u_plat = M4U_MT2712, - .has_4gb_mode = true, - .has_bclk = true, - .has_vld_pa_rng = true, + .flags = HAS_4GB_MODE | + HAS_BCLK | + HAS_VLD_PA_RNG, .larbid_remap = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, }; static const struct mtk_iommu_plat_data mt8173_data = { .m4u_plat = M4U_MT8173, - .has_4gb_mode = true, - .has_bclk = true, - .reset_axi = true, + .flags = HAS_4GB_MODE | + HAS_BCLK | + RESET_AXI, .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */ }; static const struct mtk_iommu_plat_data mt8183_data = { .m4u_plat = M4U_MT8183, - .reset_axi = true, + .flags = RESET_AXI, .larbid_remap = {0, 4, 5, 6, 7, 2, 3, 1}, }; diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h index 1b6ea839b92c..7cc39f729263 100644 --- a/drivers/iommu/mtk_iommu.h +++ b/drivers/iommu/mtk_iommu.h @@ -17,6 +17,15 @@ #include <linux/spinlock.h> #include <soc/mediatek/smi.h> +#define HAS_4GB_MODE BIT(0) +/* HW will use the EMI clock if there isn't the "bclk". */ +#define HAS_BCLK BIT(1) +#define HAS_VLD_PA_RNG BIT(2) +#define RESET_AXI BIT(3) + +#define MTK_IOMMU_HAS_FLAG(pdata, _x) \ + ((((pdata)->flags) & (_x)) == (_x)) + struct mtk_iommu_suspend_reg { u32 misc_ctrl; u32 dcm_dis; @@ -36,12 +45,7 @@ enum mtk_iommu_plat { struct mtk_iommu_plat_data { enum mtk_iommu_plat m4u_plat; - bool has_4gb_mode; - - /* HW will use the EMI clock if there isn't the "bclk". */ - bool has_bclk; - bool has_vld_pa_rng; - bool reset_axi; + u32 flags; unsigned char larbid_remap[MTK_LARB_NR_MAX]; };
Given the fact that we are adding more and more plat_data bool values, it would make sense to use a u32 flags register and add the appropriate macro definitions to set and check for a flag present. No functional change. Suggested-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Chao Hao <chao.hao@mediatek.com> --- drivers/iommu/mtk_iommu.c | 23 ++++++++++++----------- drivers/iommu/mtk_iommu.h | 16 ++++++++++------ 2 files changed, 22 insertions(+), 17 deletions(-)