| Message ID | 20200623042501.47065-1-ljp@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] target/ppc: add vmsumudm vmsumcud instructions | expand |
On Mon, Jun 22, 2020 at 11:25:01PM -0500, Lijun Pan wrote: > vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo > VA-form. > vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned > Doubleword VA-form. If this is only in ISA 3.1, shouldn't it be conditional on some instruction flag for that? SHould this maybe be integrated into your other series of ISA 3.1 instructions. > > Signed-off-by: Lijun Pan <ljp@linux.ibm.com> > --- > v3: implement vmsumudm/vmsumcud through int128 functions, > suggested by Richard Henderson. > > disas/ppc.c | 2 ++ > target/ppc/helper.h | 4 ++- > target/ppc/int_helper.c | 49 ++++++++++++++++++++++++++++- > target/ppc/translate.c | 1 - > target/ppc/translate/vmx-impl.inc.c | 39 ++++++++++++----------- > target/ppc/translate/vmx-ops.inc.c | 2 ++ > 6 files changed, 76 insertions(+), 21 deletions(-) > > diff --git a/disas/ppc.c b/disas/ppc.c > index 63e97cfe1d..bd76fae4c4 100644 > --- a/disas/ppc.c > +++ b/disas/ppc.c > @@ -2261,7 +2261,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { > { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, > { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, > { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, > +{ "vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, > { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, > +{ "vmsumcud", VXA(4, 23), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, > { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, > { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, > { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, > diff --git a/target/ppc/helper.h b/target/ppc/helper.h > index 2dfa1c6942..d540e8f30b 100644 > --- a/target/ppc/helper.h > +++ b/target/ppc/helper.h > @@ -263,10 +263,12 @@ DEF_HELPER_3(vpkpx, void, avr, avr, avr) > DEF_HELPER_5(vmhaddshs, void, env, avr, avr, avr, avr) > DEF_HELPER_5(vmhraddshs, void, env, avr, avr, avr, avr) > DEF_HELPER_5(vmsumuhm, void, env, avr, avr, avr, avr) > +DEF_HELPER_5(vmsumudm, void, env, avr, avr, avr, avr) > DEF_HELPER_5(vmsumuhs, void, env, avr, avr, avr, avr) > DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr) > DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr) > -DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr) > +DEF_HELPER_5(vmsumcud, void, env, avr, avr, avr, avr) > +DEF_HELPER_5(vmladduhm, void, env, avr, avr, avr, avr) > DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32) > DEF_HELPER_FLAGS_1(mfvscr, TCG_CALL_NO_RWG, i32, env) > DEF_HELPER_3(lvebx, void, env, avr, tl) > diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c > index be53cd6f68..37ea343cb3 100644 > --- a/target/ppc/int_helper.c > +++ b/target/ppc/int_helper.c > @@ -926,7 +926,8 @@ void helper_vmhraddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, > } > } > > -void helper_vmladduhm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) > +void helper_vmladduhm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, > + ppc_avr_t *b, ppc_avr_t *c) > { > int i; > > @@ -1064,6 +1065,52 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, > } > } > > +void helper_vmsumudm(CPUPPCState *env, ppc_avr_t *r, > + ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) > +{ > + Int128 sum; > + uint64_t lo, hi; > + > + sum = int128_make128(c->VsrD(1), c->VsrD(0)); > + > + mulu64(&lo, &hi, a->VsrD(0), b->VsrD(0)); > + sum = int128_add(sum, int128_make128(lo, hi)); > + > + mulu64(&lo, &hi, a->VsrD(1), b->VsrD(1)); > + sum = int128_add(sum, int128_make128(lo, hi)); > + > + r->VsrD(0) = int128_gethi(sum); > + r->VsrD(1) = int128_getlo(sum); > +} > + > +void helper_vmsumcud(CPUPPCState *env, ppc_avr_t *r, > + ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) > +{ > + Int128 sum; > + uint64_t p1lo, p1hi, p2lo, p2hi; > + > + mulu64(&p1lo, &p1hi, a->VsrD(0), b->VsrD(0)); > + mulu64(&p2lo, &p2hi, a->VsrD(1), b->VsrD(1)); > + > + /* Sum lowest 64-bit elements. */ > + sum = int128_make128(c->VsrD(1), 0); > + sum = int128_add(sum, int128_make128(p1lo, 0)); > + sum = int128_add(sum, int128_make128(p2lo, 0)); > + > + /* > + * Discard low 64-bits, leaving the carry into bit 64. > + * Then sum the higher 64-bit elements. > + */ > + sum = int128_rshift(sum, 64); > + sum = int128_add(sum, int128_make128(c->VsrD(0), 0)); > + sum = int128_add(sum, int128_make128(p1hi, 0)); > + sum = int128_add(sum, int128_make128(p2hi, 0)); > + > + /* The result is only the carry into bits 64 & 65. */ > + r->VsrD(1) = int128_gethi(sum); > + r->VsrD(0) = 0; > +} > + > #define VMUL_DO_EVN(name, mul_element, mul_access, prod_access, cast) \ > void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ > { \ > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 4ce3d664b5..35ff1aa77e 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -7281,7 +7281,6 @@ GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), > GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), > GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), > GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), > -GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), > #if defined(TARGET_PPC64) > GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, > PPC2_ISA300), > diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c > index 403ed3a01c..520b49a773 100644 > --- a/target/ppc/translate/vmx-impl.inc.c > +++ b/target/ppc/translate/vmx-impl.inc.c > @@ -1248,6 +1248,25 @@ static void gen_vsldoi(DisasContext *ctx) > tcg_temp_free_i32(sh); > } > > +#define GEN_VAFORM(name, opc2) \ > +static void glue(gen_, name)(DisasContext *ctx) \ > +{ \ > + TCGv_ptr ra, rb, rc, rd; \ > + if (unlikely(!ctx->altivec_enabled)) { \ > + gen_exception(ctx, POWERPC_EXCP_VPU); \ > + return; \ > + } \ > + ra = gen_avr_ptr(rA(ctx->opcode)); \ > + rb = gen_avr_ptr(rB(ctx->opcode)); \ > + rc = gen_avr_ptr(rC(ctx->opcode)); \ > + rd = gen_avr_ptr(rD(ctx->opcode)); \ > + gen_helper_##name(cpu_env, rd, ra, rb, rc); \ > + tcg_temp_free_ptr(ra); \ > + tcg_temp_free_ptr(rb); \ > + tcg_temp_free_ptr(rc); \ > + tcg_temp_free_ptr(rd); \ > +} > + > #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ > static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ > { \ > @@ -1272,24 +1291,8 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ > } > > GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) > - > -static void gen_vmladduhm(DisasContext *ctx) > -{ > - TCGv_ptr ra, rb, rc, rd; > - if (unlikely(!ctx->altivec_enabled)) { > - gen_exception(ctx, POWERPC_EXCP_VPU); > - return; > - } > - ra = gen_avr_ptr(rA(ctx->opcode)); > - rb = gen_avr_ptr(rB(ctx->opcode)); > - rc = gen_avr_ptr(rC(ctx->opcode)); > - rd = gen_avr_ptr(rD(ctx->opcode)); > - gen_helper_vmladduhm(rd, ra, rb, rc); > - tcg_temp_free_ptr(ra); > - tcg_temp_free_ptr(rb); > - tcg_temp_free_ptr(rc); > - tcg_temp_free_ptr(rd); > -} > +GEN_VAFORM(vmsumcud, 11) > +GEN_VAFORM_PAIRED(vmladduhm, vmsumudm, 17) > > static void gen_vpermr(DisasContext *ctx) > { > diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c > index 84e05fb827..aee23e31c6 100644 > --- a/target/ppc/translate/vmx-ops.inc.c > +++ b/target/ppc/translate/vmx-ops.inc.c > @@ -276,6 +276,8 @@ GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), > GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), > GEN_VAFORM_PAIRED(vsel, vperm, 21), > GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), > +GEN_HANDLER(vmsumcud, 0x4, 11, 0xFF, 0x00000000, PPC_ALTIVEC), > +GEN_VAFORM_PAIRED(vmladduhm, vmsumudm, 17), > > GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207), > GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
> On Jul 6, 2020, at 2:53 AM, David Gibson <david@gibson.dropbear.id.au> wrote: > > On Mon, Jun 22, 2020 at 11:25:01PM -0500, Lijun Pan wrote: >> vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo >> VA-form. >> vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned >> Doubleword VA-form. > > If this is only in ISA 3.1, shouldn't it be conditional on some > instruction flag for that? I will change to, --- a/target/ppc/translate/vmx-ops.inc.c +++ b/target/ppc/translate/vmx-ops.inc.c @@ -276,6 +276,8 @@ GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), GEN_VAFORM_PAIRED(vsel, vperm, 21), GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), +GEN_HANDLER(vmsumcud, 0x4, 11, 0xFF, 0x00000000, PPC2_ISA310), > > SHould this maybe be integrated into your other series of ISA 3.1 > instructions. I can do that. I know some of the v4 patches of the ISA3.1 sereies are already accepted. When I resend the v5 of that series, shall I include the already accepted one? or just resend the not-accepted-yet patches. > >> >> Signed-off-by: Lijun Pan <ljp@linux.ibm.com> >> --- >> v3: implement vmsumudm/vmsumcud through int128 functions, >> suggested by Richard Henderson. >> >> disas/ppc.c | 2 ++ >> target/ppc/helper.h | 4 ++- >> target/ppc/int_helper.c | 49 ++++++++++++++++++++++++++++- >> target/ppc/translate.c | 1 - >> target/ppc/translate/vmx-impl.inc.c | 39 ++++++++++++----------- >> target/ppc/translate/vmx-ops.inc.c | 2 ++ >> 6 files changed, 76 insertions(+), 21 deletions(-) >> >> diff --git a/disas/ppc.c b/disas/ppc.c >> index 63e97cfe1d..bd76fae4c4 100644 >> --- a/disas/ppc.c >> +++ b/disas/ppc.c >> @@ -2261,7 +2261,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { >> { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, >> { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, >> { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, >> +{ "vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, >> { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, >> +{ "vmsumcud", VXA(4, 23), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, >> { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, >> { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, >> { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, >> diff --git a/target/ppc/helper.h b/target/ppc/helper.h >> index 2dfa1c6942..d540e8f30b 100644 >> --- a/target/ppc/helper.h >> +++ b/target/ppc/helper.h >> @@ -263,10 +263,12 @@ DEF_HELPER_3(vpkpx, void, avr, avr, avr) >> DEF_HELPER_5(vmhaddshs, void, env, avr, avr, avr, avr) >> DEF_HELPER_5(vmhraddshs, void, env, avr, avr, avr, avr) >> DEF_HELPER_5(vmsumuhm, void, env, avr, avr, avr, avr) >> +DEF_HELPER_5(vmsumudm, void, env, avr, avr, avr, avr) >> DEF_HELPER_5(vmsumuhs, void, env, avr, avr, avr, avr) >> DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr) >> DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr) >> -DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr) >> +DEF_HELPER_5(vmsumcud, void, env, avr, avr, avr, avr) >> +DEF_HELPER_5(vmladduhm, void, env, avr, avr, avr, avr) >> DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32) >> DEF_HELPER_FLAGS_1(mfvscr, TCG_CALL_NO_RWG, i32, env) >> DEF_HELPER_3(lvebx, void, env, avr, tl) >> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c >> index be53cd6f68..37ea343cb3 100644 >> --- a/target/ppc/int_helper.c >> +++ b/target/ppc/int_helper.c >> @@ -926,7 +926,8 @@ void helper_vmhraddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, >> } >> } >> >> -void helper_vmladduhm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) >> +void helper_vmladduhm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, >> + ppc_avr_t *b, ppc_avr_t *c) >> { >> int i; >> >> @@ -1064,6 +1065,52 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, >> } >> } >> >> +void helper_vmsumudm(CPUPPCState *env, ppc_avr_t *r, >> + ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) >> +{ >> + Int128 sum; >> + uint64_t lo, hi; >> + >> + sum = int128_make128(c->VsrD(1), c->VsrD(0)); >> + >> + mulu64(&lo, &hi, a->VsrD(0), b->VsrD(0)); >> + sum = int128_add(sum, int128_make128(lo, hi)); >> + >> + mulu64(&lo, &hi, a->VsrD(1), b->VsrD(1)); >> + sum = int128_add(sum, int128_make128(lo, hi)); >> + >> + r->VsrD(0) = int128_gethi(sum); >> + r->VsrD(1) = int128_getlo(sum); >> +} >> + >> +void helper_vmsumcud(CPUPPCState *env, ppc_avr_t *r, >> + ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) >> +{ >> + Int128 sum; >> + uint64_t p1lo, p1hi, p2lo, p2hi; >> + >> + mulu64(&p1lo, &p1hi, a->VsrD(0), b->VsrD(0)); >> + mulu64(&p2lo, &p2hi, a->VsrD(1), b->VsrD(1)); >> + >> + /* Sum lowest 64-bit elements. */ >> + sum = int128_make128(c->VsrD(1), 0); >> + sum = int128_add(sum, int128_make128(p1lo, 0)); >> + sum = int128_add(sum, int128_make128(p2lo, 0)); >> + >> + /* >> + * Discard low 64-bits, leaving the carry into bit 64. >> + * Then sum the higher 64-bit elements. >> + */ >> + sum = int128_rshift(sum, 64); >> + sum = int128_add(sum, int128_make128(c->VsrD(0), 0)); >> + sum = int128_add(sum, int128_make128(p1hi, 0)); >> + sum = int128_add(sum, int128_make128(p2hi, 0)); >> + >> + /* The result is only the carry into bits 64 & 65. */ >> + r->VsrD(1) = int128_gethi(sum); >> + r->VsrD(0) = 0; >> +} >> + >> #define VMUL_DO_EVN(name, mul_element, mul_access, prod_access, cast) \ >> void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ >> { \ >> diff --git a/target/ppc/translate.c b/target/ppc/translate.c >> index 4ce3d664b5..35ff1aa77e 100644 >> --- a/target/ppc/translate.c >> +++ b/target/ppc/translate.c >> @@ -7281,7 +7281,6 @@ GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), >> GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), >> GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), >> GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), >> -GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), >> #if defined(TARGET_PPC64) >> GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, >> PPC2_ISA300), >> diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c >> index 403ed3a01c..520b49a773 100644 >> --- a/target/ppc/translate/vmx-impl.inc.c >> +++ b/target/ppc/translate/vmx-impl.inc.c >> @@ -1248,6 +1248,25 @@ static void gen_vsldoi(DisasContext *ctx) >> tcg_temp_free_i32(sh); >> } >> >> +#define GEN_VAFORM(name, opc2) \ >> +static void glue(gen_, name)(DisasContext *ctx) \ >> +{ \ >> + TCGv_ptr ra, rb, rc, rd; \ >> + if (unlikely(!ctx->altivec_enabled)) { \ >> + gen_exception(ctx, POWERPC_EXCP_VPU); \ >> + return; \ >> + } \ >> + ra = gen_avr_ptr(rA(ctx->opcode)); \ >> + rb = gen_avr_ptr(rB(ctx->opcode)); \ >> + rc = gen_avr_ptr(rC(ctx->opcode)); \ >> + rd = gen_avr_ptr(rD(ctx->opcode)); \ >> + gen_helper_##name(cpu_env, rd, ra, rb, rc); \ >> + tcg_temp_free_ptr(ra); \ >> + tcg_temp_free_ptr(rb); \ >> + tcg_temp_free_ptr(rc); \ >> + tcg_temp_free_ptr(rd); \ >> +} >> + >> #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ >> static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ >> { \ >> @@ -1272,24 +1291,8 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ >> } >> >> GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) >> - >> -static void gen_vmladduhm(DisasContext *ctx) >> -{ >> - TCGv_ptr ra, rb, rc, rd; >> - if (unlikely(!ctx->altivec_enabled)) { >> - gen_exception(ctx, POWERPC_EXCP_VPU); >> - return; >> - } >> - ra = gen_avr_ptr(rA(ctx->opcode)); >> - rb = gen_avr_ptr(rB(ctx->opcode)); >> - rc = gen_avr_ptr(rC(ctx->opcode)); >> - rd = gen_avr_ptr(rD(ctx->opcode)); >> - gen_helper_vmladduhm(rd, ra, rb, rc); >> - tcg_temp_free_ptr(ra); >> - tcg_temp_free_ptr(rb); >> - tcg_temp_free_ptr(rc); >> - tcg_temp_free_ptr(rd); >> -} >> +GEN_VAFORM(vmsumcud, 11) >> +GEN_VAFORM_PAIRED(vmladduhm, vmsumudm, 17) >> >> static void gen_vpermr(DisasContext *ctx) >> { >> diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c >> index 84e05fb827..aee23e31c6 100644 >> --- a/target/ppc/translate/vmx-ops.inc.c >> +++ b/target/ppc/translate/vmx-ops.inc.c >> @@ -276,6 +276,8 @@ GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), >> GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), >> GEN_VAFORM_PAIRED(vsel, vperm, 21), >> GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), >> +GEN_HANDLER(vmsumcud, 0x4, 11, 0xFF, 0x00000000, PPC_ALTIVEC), >> +GEN_VAFORM_PAIRED(vmladduhm, vmsumudm, 17), >> >> GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207), >> GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207), > > -- > David Gibson | I'll have my music baroque, and my code > david AT gibson.dropbear.id.au <http://gibson.dropbear.id.au/> | minimalist, thank you. NOT _the_ _other_ > | _way_ _around_! > http://www.ozlabs.org/~dgibson <http://www.ozlabs.org/~dgibson>
diff --git a/disas/ppc.c b/disas/ppc.c index 63e97cfe1d..bd76fae4c4 100644 --- a/disas/ppc.c +++ b/disas/ppc.c @@ -2261,7 +2261,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, +{ "vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, +{ "vmsumcud", VXA(4, 23), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 2dfa1c6942..d540e8f30b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -263,10 +263,12 @@ DEF_HELPER_3(vpkpx, void, avr, avr, avr) DEF_HELPER_5(vmhaddshs, void, env, avr, avr, avr, avr) DEF_HELPER_5(vmhraddshs, void, env, avr, avr, avr, avr) DEF_HELPER_5(vmsumuhm, void, env, avr, avr, avr, avr) +DEF_HELPER_5(vmsumudm, void, env, avr, avr, avr, avr) DEF_HELPER_5(vmsumuhs, void, env, avr, avr, avr, avr) DEF_HELPER_5(vmsumshm, void, env, avr, avr, avr, avr) DEF_HELPER_5(vmsumshs, void, env, avr, avr, avr, avr) -DEF_HELPER_4(vmladduhm, void, avr, avr, avr, avr) +DEF_HELPER_5(vmsumcud, void, env, avr, avr, avr, avr) +DEF_HELPER_5(vmladduhm, void, env, avr, avr, avr, avr) DEF_HELPER_FLAGS_2(mtvscr, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_1(mfvscr, TCG_CALL_NO_RWG, i32, env) DEF_HELPER_3(lvebx, void, env, avr, tl) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index be53cd6f68..37ea343cb3 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -926,7 +926,8 @@ void helper_vmhraddshs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, } } -void helper_vmladduhm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_vmladduhm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, + ppc_avr_t *b, ppc_avr_t *c) { int i; @@ -1064,6 +1065,52 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, } } +void helper_vmsumudm(CPUPPCState *env, ppc_avr_t *r, + ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +{ + Int128 sum; + uint64_t lo, hi; + + sum = int128_make128(c->VsrD(1), c->VsrD(0)); + + mulu64(&lo, &hi, a->VsrD(0), b->VsrD(0)); + sum = int128_add(sum, int128_make128(lo, hi)); + + mulu64(&lo, &hi, a->VsrD(1), b->VsrD(1)); + sum = int128_add(sum, int128_make128(lo, hi)); + + r->VsrD(0) = int128_gethi(sum); + r->VsrD(1) = int128_getlo(sum); +} + +void helper_vmsumcud(CPUPPCState *env, ppc_avr_t *r, + ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +{ + Int128 sum; + uint64_t p1lo, p1hi, p2lo, p2hi; + + mulu64(&p1lo, &p1hi, a->VsrD(0), b->VsrD(0)); + mulu64(&p2lo, &p2hi, a->VsrD(1), b->VsrD(1)); + + /* Sum lowest 64-bit elements. */ + sum = int128_make128(c->VsrD(1), 0); + sum = int128_add(sum, int128_make128(p1lo, 0)); + sum = int128_add(sum, int128_make128(p2lo, 0)); + + /* + * Discard low 64-bits, leaving the carry into bit 64. + * Then sum the higher 64-bit elements. + */ + sum = int128_rshift(sum, 64); + sum = int128_add(sum, int128_make128(c->VsrD(0), 0)); + sum = int128_add(sum, int128_make128(p1hi, 0)); + sum = int128_add(sum, int128_make128(p2hi, 0)); + + /* The result is only the carry into bits 64 & 65. */ + r->VsrD(1) = int128_gethi(sum); + r->VsrD(0) = 0; +} + #define VMUL_DO_EVN(name, mul_element, mul_access, prod_access, cast) \ void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ { \ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4ce3d664b5..35ff1aa77e 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7281,7 +7281,6 @@ GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), -GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), #if defined(TARGET_PPC64) GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c index 403ed3a01c..520b49a773 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -1248,6 +1248,25 @@ static void gen_vsldoi(DisasContext *ctx) tcg_temp_free_i32(sh); } +#define GEN_VAFORM(name, opc2) \ +static void glue(gen_, name)(DisasContext *ctx) \ +{ \ + TCGv_ptr ra, rb, rc, rd; \ + if (unlikely(!ctx->altivec_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_VPU); \ + return; \ + } \ + ra = gen_avr_ptr(rA(ctx->opcode)); \ + rb = gen_avr_ptr(rB(ctx->opcode)); \ + rc = gen_avr_ptr(rC(ctx->opcode)); \ + rd = gen_avr_ptr(rD(ctx->opcode)); \ + gen_helper_##name(cpu_env, rd, ra, rb, rc); \ + tcg_temp_free_ptr(ra); \ + tcg_temp_free_ptr(rb); \ + tcg_temp_free_ptr(rc); \ + tcg_temp_free_ptr(rd); \ +} + #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ { \ @@ -1272,24 +1291,8 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ } GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16) - -static void gen_vmladduhm(DisasContext *ctx) -{ - TCGv_ptr ra, rb, rc, rd; - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } - ra = gen_avr_ptr(rA(ctx->opcode)); - rb = gen_avr_ptr(rB(ctx->opcode)); - rc = gen_avr_ptr(rC(ctx->opcode)); - rd = gen_avr_ptr(rD(ctx->opcode)); - gen_helper_vmladduhm(rd, ra, rb, rc); - tcg_temp_free_ptr(ra); - tcg_temp_free_ptr(rb); - tcg_temp_free_ptr(rc); - tcg_temp_free_ptr(rd); -} +GEN_VAFORM(vmsumcud, 11) +GEN_VAFORM_PAIRED(vmladduhm, vmsumudm, 17) static void gen_vpermr(DisasContext *ctx) { diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c index 84e05fb827..aee23e31c6 100644 --- a/target/ppc/translate/vmx-ops.inc.c +++ b/target/ppc/translate/vmx-ops.inc.c @@ -276,6 +276,8 @@ GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19), GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20), GEN_VAFORM_PAIRED(vsel, vperm, 21), GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23), +GEN_HANDLER(vmsumcud, 0x4, 11, 0xFF, 0x00000000, PPC_ALTIVEC), +GEN_VAFORM_PAIRED(vmladduhm, vmsumudm, 17), GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207), GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
vmsumudm (Power ISA 3.0) - Vector Multiply-Sum Unsigned Doubleword Modulo VA-form. vmsumcud (Power ISA 3.1) - Vector Multiply-Sum & write Carry-out Unsigned Doubleword VA-form. Signed-off-by: Lijun Pan <ljp@linux.ibm.com> --- v3: implement vmsumudm/vmsumcud through int128 functions, suggested by Richard Henderson. disas/ppc.c | 2 ++ target/ppc/helper.h | 4 ++- target/ppc/int_helper.c | 49 ++++++++++++++++++++++++++++- target/ppc/translate.c | 1 - target/ppc/translate/vmx-impl.inc.c | 39 ++++++++++++----------- target/ppc/translate/vmx-ops.inc.c | 2 ++ 6 files changed, 76 insertions(+), 21 deletions(-)