| Message ID | 1593762506-32680-1-git-send-email-rnayak@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] pinctrl: qcom: sc7180: Make gpio28 non wakeup capable for google,lazor | expand |
Hi, On Fri, Jul 3, 2020 at 12:49 AM Rajendra Nayak <rnayak@codeaurora.org> wrote: > > The PDC irqchip driver currently does not handle dual-edge interrupts, > and we have google,lazor board with sc7180 designed to configure gpio28 > as a dual-edge interrupt. This interrupt is however not expected to be > wakeup capable on this board, so an easy way to fix this, seems to be to > make this gpio non wakeup capable and let TLMM handle it (which is capable > of handling dual-edge irqs) > > To be able to do so only on this board, so other boards designed with > this SoC can continue to use gpio28 as a wakeup capable one, make a > copy of msm_gpio_wakeirq_map for lazor and remove gpio28 from the > list. > > Reported-by: Jimmy Cheng-Yi Chiang <cychiang@google.com> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- > drivers/pinctrl/qcom/pinctrl-sc7180.c | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c > index 1b6465a..0668933 100644 > --- a/drivers/pinctrl/qcom/pinctrl-sc7180.c > +++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c > @@ -1135,7 +1135,24 @@ static const struct msm_gpio_wakeirq_map sc7180_pdc_map[] = { > {117, 114}, {118, 119}, > }; > > -static const struct msm_pinctrl_soc_data sc7180_pinctrl = { > +/* Dropped gpio28 from the map for the google,lazor board */ > +static const struct msm_gpio_wakeirq_map sc7180_lazor_pdc_map[] = { > + {0, 40}, {3, 50}, {4, 42}, {5, 70}, {6, 41}, {9, 35}, > + {10, 80}, {11, 51}, {16, 20}, {21, 55}, {22, 90}, {23, 21}, > + {24, 61}, {26, 52}, {30, 100}, {31, 33}, {32, 81}, > + {33, 62}, {34, 43}, {36, 91}, {37, 53}, {38, 63}, {39, 72}, > + {41, 101}, {42, 7}, {43, 34}, {45, 73}, {47, 82}, {49, 17}, > + {52, 109}, {53, 102}, {55, 92}, {56, 56}, {57, 57}, {58, 83}, > + {59, 37}, {62, 110}, {63, 111}, {64, 74}, {65, 44}, {66, 93}, > + {67, 58}, {68, 112}, {69, 32}, {70, 54}, {72, 59}, {73, 64}, > + {74, 71}, {78, 31}, {82, 30}, {85, 103}, {86, 38}, {87, 39}, > + {88, 45}, {89, 46}, {90, 47}, {91, 48}, {92, 60}, {93, 49}, > + {94, 84}, {95, 94}, {98, 65}, {101, 66}, {104, 67}, {109, 104}, > + {110, 68}, {113, 69}, {114, 113}, {115, 108}, {116, 121}, > + {117, 114}, {118, 119}, > +}; > + > +static struct msm_pinctrl_soc_data sc7180_pinctrl = { > .pins = sc7180_pins, > .npins = ARRAY_SIZE(sc7180_pins), > .functions = sc7180_functions, > @@ -1151,6 +1168,10 @@ static const struct msm_pinctrl_soc_data sc7180_pinctrl = { > > static int sc7180_pinctrl_probe(struct platform_device *pdev) > { > + if (of_machine_is_compatible("google,lazor")) { > + sc7180_pinctrl.wakeirq_map = sc7180_lazor_pdc_map; > + sc7180_pinctrl.nwakeirq_map = ARRAY_SIZE(sc7180_lazor_pdc_map); > + } As much as I want patches landed and things working, the above just doesn't feel like a viable solution. I guess it could work as a short term hack but it's going to become untenable pretty quickly. As we have more variants of this we're going to have to just keep piling more machines in here, right? ...this is also already broken for us because not all boards will have the "google,lazor" compatible. From the current Chrome OS here are the compatibles for various revs/SKUs compatible = "google,lazor-rev0", "qcom,sc7180"; compatible = "google,lazor-rev0-sku0", "qcom,sc7180"; compatible = "google,lazor", "qcom,sc7180"; compatible = "google,lazor-sku0", "qcom,sc7180"; compatible = "google,lazor-rev2", "qcom,sc7180"; ...so of the 5 boards you'll only match one of them. Maybe I'm jumping into a situation again where I'm ignorant since I haven't followed all the prior conversation, but is it really that hard to just add dual edge support to the PDC irqchip driver? ...or maybe it's just easier to change the pinctrl driver to emulate dual edge itself and that can work around the problem in the PDC? There seem to be a few samples you could copy from: $ git log --oneline --no-merges --grep=emulate drivers/pinctrl/ 3221f40b7631 pinctrl: mediatek: emulate GPIO interrupt on both-edges 5a92750133ff pinctrl: rockchip: emulate both edge triggered interrupts ...and if you look at those two commits they refer to other examples. The mediatek one says: > This follows an example of drivers/gpio/gpio-mxc.c. ...and the Rockchip one says: > implement a solution similar to pinctrl-coh901 That means you have at least 4 samples to look at? -Doug
On Mon 06 Jul 13:24 PDT 2020, Doug Anderson wrote: > Hi, > > On Fri, Jul 3, 2020 at 12:49 AM Rajendra Nayak <rnayak@codeaurora.org> wrote: > > > > The PDC irqchip driver currently does not handle dual-edge interrupts, > > and we have google,lazor board with sc7180 designed to configure gpio28 > > as a dual-edge interrupt. This interrupt is however not expected to be > > wakeup capable on this board, so an easy way to fix this, seems to be to > > make this gpio non wakeup capable and let TLMM handle it (which is capable > > of handling dual-edge irqs) > > > > To be able to do so only on this board, so other boards designed with > > this SoC can continue to use gpio28 as a wakeup capable one, make a > > copy of msm_gpio_wakeirq_map for lazor and remove gpio28 from the > > list. > > > > Reported-by: Jimmy Cheng-Yi Chiang <cychiang@google.com> > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > > --- > > drivers/pinctrl/qcom/pinctrl-sc7180.c | 23 ++++++++++++++++++++++- > > 1 file changed, 22 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c > > index 1b6465a..0668933 100644 > > --- a/drivers/pinctrl/qcom/pinctrl-sc7180.c > > +++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c > > @@ -1135,7 +1135,24 @@ static const struct msm_gpio_wakeirq_map sc7180_pdc_map[] = { > > {117, 114}, {118, 119}, > > }; > > > > -static const struct msm_pinctrl_soc_data sc7180_pinctrl = { > > +/* Dropped gpio28 from the map for the google,lazor board */ > > +static const struct msm_gpio_wakeirq_map sc7180_lazor_pdc_map[] = { > > + {0, 40}, {3, 50}, {4, 42}, {5, 70}, {6, 41}, {9, 35}, > > + {10, 80}, {11, 51}, {16, 20}, {21, 55}, {22, 90}, {23, 21}, > > + {24, 61}, {26, 52}, {30, 100}, {31, 33}, {32, 81}, > > + {33, 62}, {34, 43}, {36, 91}, {37, 53}, {38, 63}, {39, 72}, > > + {41, 101}, {42, 7}, {43, 34}, {45, 73}, {47, 82}, {49, 17}, > > + {52, 109}, {53, 102}, {55, 92}, {56, 56}, {57, 57}, {58, 83}, > > + {59, 37}, {62, 110}, {63, 111}, {64, 74}, {65, 44}, {66, 93}, > > + {67, 58}, {68, 112}, {69, 32}, {70, 54}, {72, 59}, {73, 64}, > > + {74, 71}, {78, 31}, {82, 30}, {85, 103}, {86, 38}, {87, 39}, > > + {88, 45}, {89, 46}, {90, 47}, {91, 48}, {92, 60}, {93, 49}, > > + {94, 84}, {95, 94}, {98, 65}, {101, 66}, {104, 67}, {109, 104}, > > + {110, 68}, {113, 69}, {114, 113}, {115, 108}, {116, 121}, > > + {117, 114}, {118, 119}, > > +}; > > + > > +static struct msm_pinctrl_soc_data sc7180_pinctrl = { > > .pins = sc7180_pins, > > .npins = ARRAY_SIZE(sc7180_pins), > > .functions = sc7180_functions, > > @@ -1151,6 +1168,10 @@ static const struct msm_pinctrl_soc_data sc7180_pinctrl = { > > > > static int sc7180_pinctrl_probe(struct platform_device *pdev) > > { > > + if (of_machine_is_compatible("google,lazor")) { > > + sc7180_pinctrl.wakeirq_map = sc7180_lazor_pdc_map; > > + sc7180_pinctrl.nwakeirq_map = ARRAY_SIZE(sc7180_lazor_pdc_map); > > + } > > As much as I want patches landed and things working, the above just > doesn't feel like a viable solution. I guess it could work as a short > term hack but it's going to become untenable pretty quickly. I second that. > As we > have more variants of this we're going to have to just keep piling > more machines in here, right? ...this is also already broken for us > because not all boards will have the "google,lazor" compatible. From > the current Chrome OS here are the compatibles for various revs/SKUs > > compatible = "google,lazor-rev0", "qcom,sc7180"; > compatible = "google,lazor-rev0-sku0", "qcom,sc7180"; > compatible = "google,lazor", "qcom,sc7180"; > compatible = "google,lazor-sku0", "qcom,sc7180"; > compatible = "google,lazor-rev2", "qcom,sc7180"; > > ...so of the 5 boards you'll only match one of them. > > > Maybe I'm jumping into a situation again where I'm ignorant since I > haven't followed all the prior conversation, but is it really that > hard to just add dual edge support to the PDC irqchip driver? ...or > maybe it's just easier to change the pinctrl driver to emulate dual > edge itself and that can work around the problem in the PDC? There > seem to be a few samples you could copy from: > > $ git log --oneline --no-merges --grep=emulate drivers/pinctrl/ > 3221f40b7631 pinctrl: mediatek: emulate GPIO interrupt on both-edges > 5a92750133ff pinctrl: rockchip: emulate both edge triggered interrupts > pinctrl-msm already supports emulating dual edge, but my understanding was that the problem lies in that somehow this emulation would have to be tied to or affect the PDC driver? Regards, Bjorn > ...and if you look at those two commits they refer to other examples. > The mediatek one says: > > > This follows an example of drivers/gpio/gpio-mxc.c. > > ...and the Rockchip one says: > > > implement a solution similar to pinctrl-coh901 > > That means you have at least 4 samples to look at? > > > -Doug
[].. >>> @@ -1151,6 +1168,10 @@ static const struct msm_pinctrl_soc_data sc7180_pinctrl = { >>> >>> static int sc7180_pinctrl_probe(struct platform_device *pdev) >>> { >>> + if (of_machine_is_compatible("google,lazor")) { >>> + sc7180_pinctrl.wakeirq_map = sc7180_lazor_pdc_map; >>> + sc7180_pinctrl.nwakeirq_map = ARRAY_SIZE(sc7180_lazor_pdc_map); >>> + } >> >> As much as I want patches landed and things working, the above just >> doesn't feel like a viable solution. I guess it could work as a short >> term hack but it's going to become untenable pretty quickly. > > I second that. > >> As we >> have more variants of this we're going to have to just keep piling >> more machines in here, right? ...this is also already broken for us >> because not all boards will have the "google,lazor" compatible. From >> the current Chrome OS here are the compatibles for various revs/SKUs >> >> compatible = "google,lazor-rev0", "qcom,sc7180"; >> compatible = "google,lazor-rev0-sku0", "qcom,sc7180"; >> compatible = "google,lazor", "qcom,sc7180"; >> compatible = "google,lazor-sku0", "qcom,sc7180"; >> compatible = "google,lazor-rev2", "qcom,sc7180"; >> >> ...so of the 5 boards you'll only match one of them. >> >> >> Maybe I'm jumping into a situation again where I'm ignorant since I >> haven't followed all the prior conversation, but is it really that >> hard to just add dual edge support to the PDC irqchip driver? ...or FWIK, this is really a PDC hardware issue (with the specific IP rev that exists on sc7180) so working it around in SW could get ugly. >> maybe it's just easier to change the pinctrl driver to emulate dual >> edge itself and that can work around the problem in the PDC? There >> seem to be a few samples you could copy from: >> >> $ git log --oneline --no-merges --grep=emulate drivers/pinctrl/ >> 3221f40b7631 pinctrl: mediatek: emulate GPIO interrupt on both-edges >> 5a92750133ff pinctrl: rockchip: emulate both edge triggered interrupts >> > > pinctrl-msm already supports emulating dual edge, but my understanding > was that the problem lies in that somehow this emulation would have to > be tied to or affect the PDC driver? yes, thats correct, pinctrl-msm already supports it, the problem lies in the fact that PDC does not. This patch, infact was trying to fix the issue by removing all PDC involvement for gpio28 and making pinctrl-msm in charge of it.
Hi, On Mon, Jul 6, 2020 at 9:52 PM Rajendra Nayak <rnayak@codeaurora.org> wrote: > > > [].. > > >>> @@ -1151,6 +1168,10 @@ static const struct msm_pinctrl_soc_data sc7180_pinctrl = { > >>> > >>> static int sc7180_pinctrl_probe(struct platform_device *pdev) > >>> { > >>> + if (of_machine_is_compatible("google,lazor")) { > >>> + sc7180_pinctrl.wakeirq_map = sc7180_lazor_pdc_map; > >>> + sc7180_pinctrl.nwakeirq_map = ARRAY_SIZE(sc7180_lazor_pdc_map); > >>> + } > >> > >> As much as I want patches landed and things working, the above just > >> doesn't feel like a viable solution. I guess it could work as a short > >> term hack but it's going to become untenable pretty quickly. > > > > I second that. > > > >> As we > >> have more variants of this we're going to have to just keep piling > >> more machines in here, right? ...this is also already broken for us > >> because not all boards will have the "google,lazor" compatible. From > >> the current Chrome OS here are the compatibles for various revs/SKUs > >> > >> compatible = "google,lazor-rev0", "qcom,sc7180"; > >> compatible = "google,lazor-rev0-sku0", "qcom,sc7180"; > >> compatible = "google,lazor", "qcom,sc7180"; > >> compatible = "google,lazor-sku0", "qcom,sc7180"; > >> compatible = "google,lazor-rev2", "qcom,sc7180"; > >> > >> ...so of the 5 boards you'll only match one of them. > >> > >> > >> Maybe I'm jumping into a situation again where I'm ignorant since I > >> haven't followed all the prior conversation, but is it really that > >> hard to just add dual edge support to the PDC irqchip driver? ...or > > FWIK, this is really a PDC hardware issue (with the specific IP rev that exists > on sc7180) so working it around in SW could get ugly. Ugh. I guess it's ugly because the workaround would need to be in the PDC driver but to properly do the workaround you need to be able to read the state of the pin from the PDC driver? ...and I guess you can't do that with the PDC register space so you'd either need to violate a layer or 3 of abstraction and snarf into the GPIO register space from the PDC driver or you'd have to provide some sort of API access from the PDC back down to the GPIO driver? -- Actually, though, I'm still not sure why this would need to be in the PDC driver. Sure, you can't just magically re-use the existing dual-edge emulation in pinctrl-msm.c, but you can add some new dual-edge emulation for when your parent handles your interrupts, can't you? As per usually, I'm talking out of my rear end, but I sorta imagine: 1. At the head of msm_gpio_irq_set_type() if you detect that "skip_wake_irqs" is set and you're on an SoC with this hardware errata then you do a loop much like the one in msm_gpio_update_dual_edge_pos() except that instead of changing the polarity with msm_writel_intr_cfg() you change the polarity with "irq_chip_set_type_parent()". 2. At the head of msm_gpio_irq_ack() you make the same function call if "skip_wake_irqs" is set and you're on an SoC with this hardware errata. It doesn't feel all that ugly to me, assuming I'm understanding it correctly. ...or maybe you can tell me why it'd be harder than that? > >> maybe it's just easier to change the pinctrl driver to emulate dual > >> edge itself and that can work around the problem in the PDC? There > >> seem to be a few samples you could copy from: > >> > >> $ git log --oneline --no-merges --grep=emulate drivers/pinctrl/ > >> 3221f40b7631 pinctrl: mediatek: emulate GPIO interrupt on both-edges > >> 5a92750133ff pinctrl: rockchip: emulate both edge triggered interrupts > >> > > > > pinctrl-msm already supports emulating dual edge, but my understanding > > was that the problem lies in that somehow this emulation would have to > > be tied to or affect the PDC driver? > > yes, thats correct, pinctrl-msm already supports it, the problem lies > in the fact that PDC does not. This patch, infact was trying to fix the > issue by removing all PDC involvement for gpio28 and making pinctrl-msm > in charge of it. If we're going to try to do this, I think we're stuck with one of these: 1. A really really long list that we keep jamming more boards into. 2. Add an entry at the top-level device tree compatible to all affected boards _just_ for this purpose. Seems ugly since we don't need it for any other reasons. 3. Add some sort of property to the pinctrl node on these boards. Seems ugly since conceivably this _could_ be worked around in software. I don't really like any of those options, so I'm really hoping we can find out how to get a workaround in... -Doug
Hi, On Tue, Jul 7, 2020 at 4:03 PM Doug Anderson <dianders@chromium.org> wrote: > > Hi, > > On Mon, Jul 6, 2020 at 9:52 PM Rajendra Nayak <rnayak@codeaurora.org> wrote: > > > > > > [].. > > > > >>> @@ -1151,6 +1168,10 @@ static const struct msm_pinctrl_soc_data sc7180_pinctrl = { > > >>> > > >>> static int sc7180_pinctrl_probe(struct platform_device *pdev) > > >>> { > > >>> + if (of_machine_is_compatible("google,lazor")) { > > >>> + sc7180_pinctrl.wakeirq_map = sc7180_lazor_pdc_map; > > >>> + sc7180_pinctrl.nwakeirq_map = ARRAY_SIZE(sc7180_lazor_pdc_map); > > >>> + } > > >> > > >> As much as I want patches landed and things working, the above just > > >> doesn't feel like a viable solution. I guess it could work as a short > > >> term hack but it's going to become untenable pretty quickly. > > > > > > I second that. > > > > > >> As we > > >> have more variants of this we're going to have to just keep piling > > >> more machines in here, right? ...this is also already broken for us > > >> because not all boards will have the "google,lazor" compatible. From > > >> the current Chrome OS here are the compatibles for various revs/SKUs > > >> > > >> compatible = "google,lazor-rev0", "qcom,sc7180"; > > >> compatible = "google,lazor-rev0-sku0", "qcom,sc7180"; > > >> compatible = "google,lazor", "qcom,sc7180"; > > >> compatible = "google,lazor-sku0", "qcom,sc7180"; > > >> compatible = "google,lazor-rev2", "qcom,sc7180"; > > >> > > >> ...so of the 5 boards you'll only match one of them. > > >> > > >> > > >> Maybe I'm jumping into a situation again where I'm ignorant since I > > >> haven't followed all the prior conversation, but is it really that > > >> hard to just add dual edge support to the PDC irqchip driver? ...or > > > > FWIK, this is really a PDC hardware issue (with the specific IP rev that exists > > on sc7180) so working it around in SW could get ugly. > > Ugh. I guess it's ugly because the workaround would need to be in the > PDC driver but to properly do the workaround you need to be able to > read the state of the pin from the PDC driver? ...and I guess you > can't do that with the PDC register space so you'd either need to > violate a layer or 3 of abstraction and snarf into the GPIO register > space from the PDC driver or you'd have to provide some sort of API > access from the PDC back down to the GPIO driver? > > -- > > Actually, though, I'm still not sure why this would need to be in the > PDC driver. Sure, you can't just magically re-use the existing > dual-edge emulation in pinctrl-msm.c, but you can add some new > dual-edge emulation for when your parent handles your interrupts, > can't you? As per usually, I'm talking out of my rear end, but I > sorta imagine: > > 1. At the head of msm_gpio_irq_set_type() if you detect that > "skip_wake_irqs" is set and you're on an SoC with this hardware errata > then you do a loop much like the one in > msm_gpio_update_dual_edge_pos() except that instead of changing the > polarity with msm_writel_intr_cfg() you change the polarity with > "irq_chip_set_type_parent()". > > 2. At the head of msm_gpio_irq_ack() you make the same function call > if "skip_wake_irqs" is set and you're on an SoC with this hardware > errata. > > It doesn't feel all that ugly to me, assuming I'm understanding it > correctly. ...or maybe you can tell me why it'd be harder than that? So I REALLY don't know what I'm doing and this is very rough and probably all sorts of illegal (maybe?), but in the limited testing I was able to do it seemed to work: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/2285815 WIP: proof of concept workaround for PDC wakeup problem If there's anything worthwhile to steal from that, please feel free and post your own patch based on it. :-) -Doug
Hi, On 7/8/2020 4:33 AM, Doug Anderson wrote: > Hi, > > On Mon, Jul 6, 2020 at 9:52 PM Rajendra Nayak <rnayak@codeaurora.org> wrote: >> >> [].. >> >>>>> @@ -1151,6 +1168,10 @@ static const struct msm_pinctrl_soc_data sc7180_pinctrl = { >>>>> >>>>> static int sc7180_pinctrl_probe(struct platform_device *pdev) >>>>> { >>>>> + if (of_machine_is_compatible("google,lazor")) { >>>>> + sc7180_pinctrl.wakeirq_map = sc7180_lazor_pdc_map; >>>>> + sc7180_pinctrl.nwakeirq_map = ARRAY_SIZE(sc7180_lazor_pdc_map); >>>>> + } >>>> As much as I want patches landed and things working, the above just >>>> doesn't feel like a viable solution. I guess it could work as a short >>>> term hack but it's going to become untenable pretty quickly. >>> I second that. >>> >>>> As we >>>> have more variants of this we're going to have to just keep piling >>>> more machines in here, right? ...this is also already broken for us >>>> because not all boards will have the "google,lazor" compatible. From >>>> the current Chrome OS here are the compatibles for various revs/SKUs >>>> >>>> compatible = "google,lazor-rev0", "qcom,sc7180"; >>>> compatible = "google,lazor-rev0-sku0", "qcom,sc7180"; >>>> compatible = "google,lazor", "qcom,sc7180"; >>>> compatible = "google,lazor-sku0", "qcom,sc7180"; >>>> compatible = "google,lazor-rev2", "qcom,sc7180"; >>>> >>>> ...so of the 5 boards you'll only match one of them. >>>> >>>> >>>> Maybe I'm jumping into a situation again where I'm ignorant since I >>>> haven't followed all the prior conversation, but is it really that >>>> hard to just add dual edge support to the PDC irqchip driver? ...or >> FWIK, this is really a PDC hardware issue (with the specific IP rev that exists >> on sc7180) so working it around in SW could get ugly. > Ugh. I guess it's ugly because the workaround would need to be in the > PDC driver but to properly do the workaround you need to be able to > read the state of the pin from the PDC driver? ...and I guess you > can't do that with the PDC register space so you'd either need to > violate a layer or 3 of abstraction and snarf into the GPIO register > space from the PDC driver or you'd have to provide some sort of API > access from the PDC back down to the GPIO driver? > > -- > > Actually, though, I'm still not sure why this would need to be in the > PDC driver. Sure, you can't just magically re-use the existing > dual-edge emulation in pinctrl-msm.c, but you can add some new > dual-edge emulation for when your parent handles your interrupts, > can't you? As per usually, I'm talking out of my rear end, but I > sorta imagine: > > 1. At the head of msm_gpio_irq_set_type() if you detect that > "skip_wake_irqs" is set and you're on an SoC with this hardware errata > then you do a loop much like the one in > msm_gpio_update_dual_edge_pos() except that instead of changing the > polarity with msm_writel_intr_cfg() you change the polarity with > "irq_chip_set_type_parent()". > > 2. At the head of msm_gpio_irq_ack() you make the same function call > if "skip_wake_irqs" is set and you're on an SoC with this hardware > errata. > > It doesn't feel all that ugly to me, assuming I'm understanding it > correctly. ...or maybe you can tell me why it'd be harder than that? > > >>>> maybe it's just easier to change the pinctrl driver to emulate dual >>>> edge itself and that can work around the problem in the PDC? There >>>> seem to be a few samples you could copy from: >>>> >>>> $ git log --oneline --no-merges --grep=emulate drivers/pinctrl/ >>>> 3221f40b7631 pinctrl: mediatek: emulate GPIO interrupt on both-edges >>>> 5a92750133ff pinctrl: rockchip: emulate both edge triggered interrupts >>>> >>> pinctrl-msm already supports emulating dual edge, but my understanding >>> was that the problem lies in that somehow this emulation would have to >>> be tied to or affect the PDC driver? >> yes, thats correct, pinctrl-msm already supports it, the problem lies >> in the fact that PDC does not. This patch, infact was trying to fix the >> issue by removing all PDC involvement for gpio28 and making pinctrl-msm >> in charge of it. > If we're going to try to do this, I think we're stuck with one of these: > > 1. A really really long list that we keep jamming more boards into. > > 2. Add an entry at the top-level device tree compatible to all > affected boards _just_ for this purpose. Seems ugly since we don't > need it for any other reasons. > > 3. Add some sort of property to the pinctrl node on these boards. > Seems ugly since conceivably this _could_ be worked around in > software. > > I don't really like any of those options, so I'm really hoping we can > find out how to get a workaround in... Hi Doug, The client driver here never uses/needs both the edges at a given time. Another option (clean & correct IMO) is to update the driver to request proper irq type its expecting. Lets take SD card detect GPIO for example, which uses dual edge interrupt. one edge (rising type) can be used as a card insert detect interrupt and another edge (falling type) may be used for card removal detect. The sequence of operations, IMO should be.. 1. Driver request a rising type irq to start with (the one that detects card insertion) 2. once card insertion irq comes in, the driver should change the type to falling which is expected (to detect the card removal) 3. once card removal irq comes in, it can change type to rising edge (to detect another insertion) 4. above steps (2,3) continues if above sequence is followed from drivers using dual edge IRQ, we don't need any workaround. Thanks, Maulik > > -Doug
Hi, On Tue, Jul 7, 2020 at 10:29 PM Maulik Shah <mkshah@codeaurora.org> wrote: > > Hi, > > On 7/8/2020 4:33 AM, Doug Anderson wrote: > > Hi, > > > > On Mon, Jul 6, 2020 at 9:52 PM Rajendra Nayak <rnayak@codeaurora.org> wrote: > >> > >> [].. > >> > >>>>> @@ -1151,6 +1168,10 @@ static const struct msm_pinctrl_soc_data sc7180_pinctrl = { > >>>>> > >>>>> static int sc7180_pinctrl_probe(struct platform_device *pdev) > >>>>> { > >>>>> + if (of_machine_is_compatible("google,lazor")) { > >>>>> + sc7180_pinctrl.wakeirq_map = sc7180_lazor_pdc_map; > >>>>> + sc7180_pinctrl.nwakeirq_map = ARRAY_SIZE(sc7180_lazor_pdc_map); > >>>>> + } > >>>> As much as I want patches landed and things working, the above just > >>>> doesn't feel like a viable solution. I guess it could work as a short > >>>> term hack but it's going to become untenable pretty quickly. > >>> I second that. > >>> > >>>> As we > >>>> have more variants of this we're going to have to just keep piling > >>>> more machines in here, right? ...this is also already broken for us > >>>> because not all boards will have the "google,lazor" compatible. From > >>>> the current Chrome OS here are the compatibles for various revs/SKUs > >>>> > >>>> compatible = "google,lazor-rev0", "qcom,sc7180"; > >>>> compatible = "google,lazor-rev0-sku0", "qcom,sc7180"; > >>>> compatible = "google,lazor", "qcom,sc7180"; > >>>> compatible = "google,lazor-sku0", "qcom,sc7180"; > >>>> compatible = "google,lazor-rev2", "qcom,sc7180"; > >>>> > >>>> ...so of the 5 boards you'll only match one of them. > >>>> > >>>> > >>>> Maybe I'm jumping into a situation again where I'm ignorant since I > >>>> haven't followed all the prior conversation, but is it really that > >>>> hard to just add dual edge support to the PDC irqchip driver? ...or > >> FWIK, this is really a PDC hardware issue (with the specific IP rev that exists > >> on sc7180) so working it around in SW could get ugly. > > Ugh. I guess it's ugly because the workaround would need to be in the > > PDC driver but to properly do the workaround you need to be able to > > read the state of the pin from the PDC driver? ...and I guess you > > can't do that with the PDC register space so you'd either need to > > violate a layer or 3 of abstraction and snarf into the GPIO register > > space from the PDC driver or you'd have to provide some sort of API > > access from the PDC back down to the GPIO driver? > > > > -- > > > > Actually, though, I'm still not sure why this would need to be in the > > PDC driver. Sure, you can't just magically re-use the existing > > dual-edge emulation in pinctrl-msm.c, but you can add some new > > dual-edge emulation for when your parent handles your interrupts, > > can't you? As per usually, I'm talking out of my rear end, but I > > sorta imagine: > > > > 1. At the head of msm_gpio_irq_set_type() if you detect that > > "skip_wake_irqs" is set and you're on an SoC with this hardware errata > > then you do a loop much like the one in > > msm_gpio_update_dual_edge_pos() except that instead of changing the > > polarity with msm_writel_intr_cfg() you change the polarity with > > "irq_chip_set_type_parent()". > > > > 2. At the head of msm_gpio_irq_ack() you make the same function call > > if "skip_wake_irqs" is set and you're on an SoC with this hardware > > errata. > > > > It doesn't feel all that ugly to me, assuming I'm understanding it > > correctly. ...or maybe you can tell me why it'd be harder than that? > > > > > >>>> maybe it's just easier to change the pinctrl driver to emulate dual > >>>> edge itself and that can work around the problem in the PDC? There > >>>> seem to be a few samples you could copy from: > >>>> > >>>> $ git log --oneline --no-merges --grep=emulate drivers/pinctrl/ > >>>> 3221f40b7631 pinctrl: mediatek: emulate GPIO interrupt on both-edges > >>>> 5a92750133ff pinctrl: rockchip: emulate both edge triggered interrupts > >>>> > >>> pinctrl-msm already supports emulating dual edge, but my understanding > >>> was that the problem lies in that somehow this emulation would have to > >>> be tied to or affect the PDC driver? > >> yes, thats correct, pinctrl-msm already supports it, the problem lies > >> in the fact that PDC does not. This patch, infact was trying to fix the > >> issue by removing all PDC involvement for gpio28 and making pinctrl-msm > >> in charge of it. > > If we're going to try to do this, I think we're stuck with one of these: > > > > 1. A really really long list that we keep jamming more boards into. > > > > 2. Add an entry at the top-level device tree compatible to all > > affected boards _just_ for this purpose. Seems ugly since we don't > > need it for any other reasons. > > > > 3. Add some sort of property to the pinctrl node on these boards. > > Seems ugly since conceivably this _could_ be worked around in > > software. > > > > I don't really like any of those options, so I'm really hoping we can > > find out how to get a workaround in... > Hi Doug, > > The client driver here never uses/needs both the edges at a given time. > Another option (clean & correct IMO) is to update the driver to request > proper irq type its expecting. > > Lets take SD card detect GPIO for example, which uses dual edge interrupt. > one edge (rising type) can be used as a card insert detect interrupt and > another edge (falling type) may be used for card removal detect. > > The sequence of operations, IMO should be.. > 1. Driver request a rising type irq to start with (the one that detects > card insertion) > 2. once card insertion irq comes in, the driver should change the type > to falling which is expected (to detect the card removal) > 3. once card removal irq comes in, it can change type to rising edge (to > detect another insertion) > 4. above steps (2,3) continues > > if above sequence is followed from drivers using dual edge IRQ, we don't > need any workaround. You're saying that we should make the rest of Linux change to work around the bug in your pinctrl driver? I don't think that'll fly too well with the maintainers of the other subsystems. The IRQ_TYPE_EDGE_BOTH define exists and we should support it. Was there something wrong with my proof of concept patch? Unless I get swamped with other things, my plan was to try to make that more real and post it unless someone told me why it was wrong... -Doug
Hi, On Wed, Jul 8, 2020 at 6:42 AM Doug Anderson <dianders@chromium.org> wrote: > > Was there something wrong with my proof of concept patch? Unless I > get swamped with other things, my plan was to try to make that more > real and post it unless someone told me why it was wrong... OK, I spent a bit of time poking at it and cleaning it. I _think_ this is right now: https://lore.kernel.org/r/20200708141610.1.Ie0d730120b232a86a4eac1e2909bcbec844d1766@changeid Please test and/or review. -Doug
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c index 1b6465a..0668933 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7180.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c @@ -1135,7 +1135,24 @@ static const struct msm_gpio_wakeirq_map sc7180_pdc_map[] = { {117, 114}, {118, 119}, }; -static const struct msm_pinctrl_soc_data sc7180_pinctrl = { +/* Dropped gpio28 from the map for the google,lazor board */ +static const struct msm_gpio_wakeirq_map sc7180_lazor_pdc_map[] = { + {0, 40}, {3, 50}, {4, 42}, {5, 70}, {6, 41}, {9, 35}, + {10, 80}, {11, 51}, {16, 20}, {21, 55}, {22, 90}, {23, 21}, + {24, 61}, {26, 52}, {30, 100}, {31, 33}, {32, 81}, + {33, 62}, {34, 43}, {36, 91}, {37, 53}, {38, 63}, {39, 72}, + {41, 101}, {42, 7}, {43, 34}, {45, 73}, {47, 82}, {49, 17}, + {52, 109}, {53, 102}, {55, 92}, {56, 56}, {57, 57}, {58, 83}, + {59, 37}, {62, 110}, {63, 111}, {64, 74}, {65, 44}, {66, 93}, + {67, 58}, {68, 112}, {69, 32}, {70, 54}, {72, 59}, {73, 64}, + {74, 71}, {78, 31}, {82, 30}, {85, 103}, {86, 38}, {87, 39}, + {88, 45}, {89, 46}, {90, 47}, {91, 48}, {92, 60}, {93, 49}, + {94, 84}, {95, 94}, {98, 65}, {101, 66}, {104, 67}, {109, 104}, + {110, 68}, {113, 69}, {114, 113}, {115, 108}, {116, 121}, + {117, 114}, {118, 119}, +}; + +static struct msm_pinctrl_soc_data sc7180_pinctrl = { .pins = sc7180_pins, .npins = ARRAY_SIZE(sc7180_pins), .functions = sc7180_functions, @@ -1151,6 +1168,10 @@ static const struct msm_pinctrl_soc_data sc7180_pinctrl = { static int sc7180_pinctrl_probe(struct platform_device *pdev) { + if (of_machine_is_compatible("google,lazor")) { + sc7180_pinctrl.wakeirq_map = sc7180_lazor_pdc_map; + sc7180_pinctrl.nwakeirq_map = ARRAY_SIZE(sc7180_lazor_pdc_map); + } return msm_pinctrl_probe(pdev, &sc7180_pinctrl); }
The PDC irqchip driver currently does not handle dual-edge interrupts, and we have google,lazor board with sc7180 designed to configure gpio28 as a dual-edge interrupt. This interrupt is however not expected to be wakeup capable on this board, so an easy way to fix this, seems to be to make this gpio non wakeup capable and let TLMM handle it (which is capable of handling dual-edge irqs) To be able to do so only on this board, so other boards designed with this SoC can continue to use gpio28 as a wakeup capable one, make a copy of msm_gpio_wakeirq_map for lazor and remove gpio28 from the list. Reported-by: Jimmy Cheng-Yi Chiang <cychiang@google.com> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> --- drivers/pinctrl/qcom/pinctrl-sc7180.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)