| Message ID | 20200706223009.1200-3-jonas@kwiboo.se (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm: rockchip: add NV15, NV20 and NV30 support | expand |
在 2020/7/7 6:30, Jonas Karlman 写道: > Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by the > Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399. > Also add support for 10-bit 4:4:4 format while at it. > > V2: Added NV30 support > > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> > --- > drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 29 +++++++++++++++++-- > drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 32 +++++++++++++++++---- > 3 files changed, 54 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > index c80f7d9fd13f..eb663e25ad9e 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > @@ -261,6 +261,18 @@ static bool has_rb_swapped(uint32_t format) > } > } > > +static bool is_fmt_10(uint32_t format) > +{ > + switch (format) { > + case DRM_FORMAT_NV15: > + case DRM_FORMAT_NV20: > + case DRM_FORMAT_NV30: > + return true; > + default: > + return false; > + } > +} > + > static enum vop_data_format vop_convert_format(uint32_t format) > { > switch (format) { > @@ -276,10 +288,13 @@ static enum vop_data_format vop_convert_format(uint32_t format) > case DRM_FORMAT_BGR565: > return VOP_FMT_RGB565; > case DRM_FORMAT_NV12: > + case DRM_FORMAT_NV15: > return VOP_FMT_YUV420SP; > case DRM_FORMAT_NV16: > + case DRM_FORMAT_NV20: > return VOP_FMT_YUV422SP; > case DRM_FORMAT_NV24: > + case DRM_FORMAT_NV30: > return VOP_FMT_YUV444SP; > default: > DRM_ERROR("unsupported format[%08x]\n", format); > @@ -922,7 +937,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, > dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; > dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); > > - offset = (src->x1 >> 16) * fb->format->cpp[0]; > + if (fb->format->block_w[0]) > + offset = (src->x1 >> 16) * fb->format->char_per_block[0] / > + fb->format->block_w[0]; > + else > + offset = (src->x1 >> 16) * fb->format->cpp[0]; > + > offset += (src->y1 >> 16) * fb->pitches[0]; > dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; > > @@ -948,6 +968,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, > } > > VOP_WIN_SET(vop, win, format, format); > + VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); > VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); > VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); > VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); > @@ -964,7 +985,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane, > uv_obj = fb->obj[1]; > rk_uv_obj = to_rockchip_obj(uv_obj); > > - offset = (src->x1 >> 16) * bpp / hsub; > + if (fb->format->block_w[1]) > + offset = (src->x1 >> 16) * bpp / > + fb->format->block_w[1] / hsub; > + else > + offset = (src->x1 >> 16) * bpp / hsub; > offset += (src->y1 >> 16) * fb->pitches[1] / vsub; > > dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h > index 4a2099cb582e..eab055d9b56d 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h > @@ -154,6 +154,7 @@ struct vop_win_phy { > struct vop_reg enable; > struct vop_reg gate; > struct vop_reg format; > + struct vop_reg fmt_10; > struct vop_reg rb_swap; > struct vop_reg act_info; > struct vop_reg dsp_info; > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > index 80053d91a301..2c55e1852c3d 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > @@ -50,6 +50,23 @@ static const uint32_t formats_win_full[] = { > DRM_FORMAT_NV24, > }; > > +static const uint32_t formats_win_full_10[] = { > + DRM_FORMAT_XRGB8888, > + DRM_FORMAT_ARGB8888, > + DRM_FORMAT_XBGR8888, > + DRM_FORMAT_ABGR8888, > + DRM_FORMAT_RGB888, > + DRM_FORMAT_BGR888, > + DRM_FORMAT_RGB565, > + DRM_FORMAT_BGR565, > + DRM_FORMAT_NV12, > + DRM_FORMAT_NV16, > + DRM_FORMAT_NV24, > + DRM_FORMAT_NV15, > + DRM_FORMAT_NV20, > + DRM_FORMAT_NV30, > +}; > + > static const uint64_t format_modifiers_win_full[] = { > DRM_FORMAT_MOD_LINEAR, > DRM_FORMAT_MOD_INVALID, > @@ -579,11 +596,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = { > > static const struct vop_win_phy rk3288_win01_data = { > .scl = &rk3288_win_full_scl, > - .data_formats = formats_win_full, > - .nformats = ARRAY_SIZE(formats_win_full), > + .data_formats = formats_win_full_10, > + .nformats = ARRAY_SIZE(formats_win_full_10), > .format_modifiers = format_modifiers_win_full, > .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), > .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), > + .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4), > .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), > .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), > .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), > @@ -713,11 +731,12 @@ static const struct vop_intr rk3368_vop_intr = { > > static const struct vop_win_phy rk3368_win01_data = { > .scl = &rk3288_win_full_scl, > - .data_formats = formats_win_full, > - .nformats = ARRAY_SIZE(formats_win_full), > + .data_formats = formats_win_full_10, > + .nformats = ARRAY_SIZE(formats_win_full_10), > .format_modifiers = format_modifiers_win_full, > .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0), > .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), > + .fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4), > .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), > .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), > .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22), > @@ -862,11 +881,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { > > static const struct vop_win_phy rk3399_win01_data = { > .scl = &rk3288_win_full_scl, > - .data_formats = formats_win_full, > - .nformats = ARRAY_SIZE(formats_win_full), > + .data_formats = formats_win_full_10, > + .nformats = ARRAY_SIZE(formats_win_full_10), > .format_modifiers = format_modifiers_win_full_afbc, > .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), > .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), > + .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4), > .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), > .y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22), > .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), Reviewed-by: Sandy Huang <hjc@rock-chips.com>
Hi Jonas, Am 07.07.20 um 00:30 schrieb Jonas Karlman: > Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by the > Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399. > Also add support for 10-bit 4:4:4 format while at it. > > V2: Added NV30 support > > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> > Reviewed-by: Sandy Huang <hjc@rock-chips.com> > --- > drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 29 +++++++++++++++++-- > drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 32 +++++++++++++++++---- > 3 files changed, 54 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > index c80f7d9fd13f..eb663e25ad9e 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c > @@ -261,6 +261,18 @@ static bool has_rb_swapped(uint32_t format) > } > } > > +static bool is_fmt_10(uint32_t format) > +{ > + switch (format) { > + case DRM_FORMAT_NV15: > + case DRM_FORMAT_NV20: > + case DRM_FORMAT_NV30: > + return true; > + default: > + return false; > + } > +} > + > static enum vop_data_format vop_convert_format(uint32_t format) > { > switch (format) { > @@ -276,10 +288,13 @@ static enum vop_data_format vop_convert_format(uint32_t format) > case DRM_FORMAT_BGR565: > return VOP_FMT_RGB565; > case DRM_FORMAT_NV12: > + case DRM_FORMAT_NV15: > return VOP_FMT_YUV420SP; > case DRM_FORMAT_NV16: > + case DRM_FORMAT_NV20: > return VOP_FMT_YUV422SP; > case DRM_FORMAT_NV24: > + case DRM_FORMAT_NV30: > return VOP_FMT_YUV444SP; > default: > DRM_ERROR("unsupported format[%08x]\n", format); > @@ -922,7 +937,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, > dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; > dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); > > - offset = (src->x1 >> 16) * fb->format->cpp[0]; > + if (fb->format->block_w[0]) > + offset = (src->x1 >> 16) * fb->format->char_per_block[0] / > + fb->format->block_w[0]; > + else > + offset = (src->x1 >> 16) * fb->format->cpp[0]; > + > offset += (src->y1 >> 16) * fb->pitches[0]; > dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; > > @@ -948,6 +968,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, > } > > VOP_WIN_SET(vop, win, format, format); > + VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); > VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); > VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); > VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); > @@ -964,7 +985,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane, > uv_obj = fb->obj[1]; > rk_uv_obj = to_rockchip_obj(uv_obj); > > - offset = (src->x1 >> 16) * bpp / hsub; > + if (fb->format->block_w[1]) > + offset = (src->x1 >> 16) * bpp / > + fb->format->block_w[1] / hsub; > + else > + offset = (src->x1 >> 16) * bpp / hsub; > offset += (src->y1 >> 16) * fb->pitches[1] / vsub; > > dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h > index 4a2099cb582e..eab055d9b56d 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h > @@ -154,6 +154,7 @@ struct vop_win_phy { > struct vop_reg enable; > struct vop_reg gate; > struct vop_reg format; > + struct vop_reg fmt_10; > struct vop_reg rb_swap; > struct vop_reg act_info; > struct vop_reg dsp_info; > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > index 80053d91a301..2c55e1852c3d 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > @@ -50,6 +50,23 @@ static const uint32_t formats_win_full[] = { > DRM_FORMAT_NV24, > }; > > +static const uint32_t formats_win_full_10[] = { > + DRM_FORMAT_XRGB8888, > + DRM_FORMAT_ARGB8888, > + DRM_FORMAT_XBGR8888, > + DRM_FORMAT_ABGR8888, > + DRM_FORMAT_RGB888, > + DRM_FORMAT_BGR888, > + DRM_FORMAT_RGB565, > + DRM_FORMAT_BGR565, > + DRM_FORMAT_NV12, > + DRM_FORMAT_NV16, > + DRM_FORMAT_NV24, > + DRM_FORMAT_NV15, > + DRM_FORMAT_NV20, > + DRM_FORMAT_NV30, > +}; > + > static const uint64_t format_modifiers_win_full[] = { > DRM_FORMAT_MOD_LINEAR, > DRM_FORMAT_MOD_INVALID, > @@ -579,11 +596,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = { > > static const struct vop_win_phy rk3288_win01_data = { > .scl = &rk3288_win_full_scl, > - .data_formats = formats_win_full, > - .nformats = ARRAY_SIZE(formats_win_full), > + .data_formats = formats_win_full_10, > + .nformats = ARRAY_SIZE(formats_win_full_10), > .format_modifiers = format_modifiers_win_full, > .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), > .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), > + .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4), > .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), > .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), > .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), > @@ -713,11 +731,12 @@ static const struct vop_intr rk3368_vop_intr = { > > static const struct vop_win_phy rk3368_win01_data = { > .scl = &rk3288_win_full_scl, > - .data_formats = formats_win_full, > - .nformats = ARRAY_SIZE(formats_win_full), > + .data_formats = formats_win_full_10, > + .nformats = ARRAY_SIZE(formats_win_full_10), > .format_modifiers = format_modifiers_win_full, > .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0), > .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), > + .fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4), > .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), > .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), > .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22), As per TRM/datasheet RK3368's VOP does not support 10-bit color formats. Therefore data_formats should be kept at formats_win_full here. > @@ -862,11 +881,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { > > static const struct vop_win_phy rk3399_win01_data = { > .scl = &rk3288_win_full_scl, > - .data_formats = formats_win_full, > - .nformats = ARRAY_SIZE(formats_win_full), > + .data_formats = formats_win_full_10, > + .nformats = ARRAY_SIZE(formats_win_full_10), > .format_modifiers = format_modifiers_win_full_afbc, > .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), > .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), > + .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4), > .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), > .y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22), > .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), Regards, Alex
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index c80f7d9fd13f..eb663e25ad9e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -261,6 +261,18 @@ static bool has_rb_swapped(uint32_t format) } } +static bool is_fmt_10(uint32_t format) +{ + switch (format) { + case DRM_FORMAT_NV15: + case DRM_FORMAT_NV20: + case DRM_FORMAT_NV30: + return true; + default: + return false; + } +} + static enum vop_data_format vop_convert_format(uint32_t format) { switch (format) { @@ -276,10 +288,13 @@ static enum vop_data_format vop_convert_format(uint32_t format) case DRM_FORMAT_BGR565: return VOP_FMT_RGB565; case DRM_FORMAT_NV12: + case DRM_FORMAT_NV15: return VOP_FMT_YUV420SP; case DRM_FORMAT_NV16: + case DRM_FORMAT_NV20: return VOP_FMT_YUV422SP; case DRM_FORMAT_NV24: + case DRM_FORMAT_NV30: return VOP_FMT_YUV444SP; default: DRM_ERROR("unsupported format[%08x]\n", format); @@ -922,7 +937,12 @@ static void vop_plane_atomic_update(struct drm_plane *plane, dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start; dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); - offset = (src->x1 >> 16) * fb->format->cpp[0]; + if (fb->format->block_w[0]) + offset = (src->x1 >> 16) * fb->format->char_per_block[0] / + fb->format->block_w[0]; + else + offset = (src->x1 >> 16) * fb->format->cpp[0]; + offset += (src->y1 >> 16) * fb->pitches[0]; dma_addr = rk_obj->dma_addr + offset + fb->offsets[0]; @@ -948,6 +968,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane, } VOP_WIN_SET(vop, win, format, format); + VOP_WIN_SET(vop, win, fmt_10, is_fmt_10(fb->format->format)); VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4)); VOP_WIN_SET(vop, win, yrgb_mst, dma_addr); VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv); @@ -964,7 +985,11 @@ static void vop_plane_atomic_update(struct drm_plane *plane, uv_obj = fb->obj[1]; rk_uv_obj = to_rockchip_obj(uv_obj); - offset = (src->x1 >> 16) * bpp / hsub; + if (fb->format->block_w[1]) + offset = (src->x1 >> 16) * bpp / + fb->format->block_w[1] / hsub; + else + offset = (src->x1 >> 16) * bpp / hsub; offset += (src->y1 >> 16) * fb->pitches[1] / vsub; dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1]; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 4a2099cb582e..eab055d9b56d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -154,6 +154,7 @@ struct vop_win_phy { struct vop_reg enable; struct vop_reg gate; struct vop_reg format; + struct vop_reg fmt_10; struct vop_reg rb_swap; struct vop_reg act_info; struct vop_reg dsp_info; diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c index 80053d91a301..2c55e1852c3d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c @@ -50,6 +50,23 @@ static const uint32_t formats_win_full[] = { DRM_FORMAT_NV24, }; +static const uint32_t formats_win_full_10[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_BGR565, + DRM_FORMAT_NV12, + DRM_FORMAT_NV16, + DRM_FORMAT_NV24, + DRM_FORMAT_NV15, + DRM_FORMAT_NV20, + DRM_FORMAT_NV30, +}; + static const uint64_t format_modifiers_win_full[] = { DRM_FORMAT_MOD_LINEAR, DRM_FORMAT_MOD_INVALID, @@ -579,11 +596,12 @@ static const struct vop_scl_regs rk3288_win_full_scl = { static const struct vop_win_phy rk3288_win01_data = { .scl = &rk3288_win_full_scl, - .data_formats = formats_win_full, - .nformats = ARRAY_SIZE(formats_win_full), + .data_formats = formats_win_full_10, + .nformats = ARRAY_SIZE(formats_win_full_10), .format_modifiers = format_modifiers_win_full, .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), + .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4), .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), @@ -713,11 +731,12 @@ static const struct vop_intr rk3368_vop_intr = { static const struct vop_win_phy rk3368_win01_data = { .scl = &rk3288_win_full_scl, - .data_formats = formats_win_full, - .nformats = ARRAY_SIZE(formats_win_full), + .data_formats = formats_win_full_10, + .nformats = ARRAY_SIZE(formats_win_full_10), .format_modifiers = format_modifiers_win_full, .enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0), .format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1), + .fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4), .rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12), .x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21), .y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22), @@ -862,11 +881,12 @@ static const struct vop_win_yuv2yuv_data rk3399_vop_big_win_yuv2yuv_data[] = { static const struct vop_win_phy rk3399_win01_data = { .scl = &rk3288_win_full_scl, - .data_formats = formats_win_full, - .nformats = ARRAY_SIZE(formats_win_full), + .data_formats = formats_win_full_10, + .nformats = ARRAY_SIZE(formats_win_full_10), .format_modifiers = format_modifiers_win_full_afbc, .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), + .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4), .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), .y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22), .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
Add support for displaying 10-bit 4:2:0 and 4:2:2 formats produced by the Rockchip Video Decoder on RK322X, RK3288, RK3328, RK3368 and RK3399. Also add support for 10-bit 4:4:4 format while at it. V2: Added NV30 support Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 29 +++++++++++++++++-- drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 + drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 32 +++++++++++++++++---- 3 files changed, 54 insertions(+), 8 deletions(-)