| Message ID | 20200623183030.26591-13-p.yadav@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mtd: spi-nor: add xSPI Octal DTR support | expand |
On 6/23/20 9:30 PM, Pratyush Yadav wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > A Soft Reset sequence will return the flash to Power-on-Reset (POR) > state. It consists of two commands: Soft Reset Enable and Soft Reset. > Find out if the sequence is supported from BFPT DWORD 16. > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > --- > drivers/mtd/spi-nor/core.h | 1 + > drivers/mtd/spi-nor/sfdp.c | 4 ++++ > drivers/mtd/spi-nor/sfdp.h | 2 ++ > 3 files changed, 7 insertions(+) > > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h > index 6338d32a0d77..79ce952c0539 100644 > --- a/drivers/mtd/spi-nor/core.h > +++ b/drivers/mtd/spi-nor/core.h > @@ -26,6 +26,7 @@ enum spi_nor_option_flags { > SNOR_F_HAS_SR_TB_BIT6 = BIT(11), > SNOR_F_HAS_4BIT_BP = BIT(12), > SNOR_F_HAS_SR_BP3_BIT6 = BIT(13), > + SNOR_F_SOFT_RESET = BIT(14), > }; > > struct spi_nor_read_command { > diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c > index 7983ff431346..8e0741d8bfd3 100644 > --- a/drivers/mtd/spi-nor/sfdp.c > +++ b/drivers/mtd/spi-nor/sfdp.c > @@ -616,6 +616,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, > break; > } > > + /* Soft Reset support. */ > + if (bfpt.dwords[BFPT_DWORD(16)] & BFPT_DWORD16_SOFT_RST) this can be improved. There are multiple reset methods described and you're addressing just one of them. > + nor->flags |= SNOR_F_SOFT_RESET; > + > /* Stop here if not JESD216 rev C or later. */ > if (bfpt_header->length == BFPT_DWORD_MAX_JESD216B) > return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, > diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h > index 6d7243067252..8ae55e98084e 100644 > --- a/drivers/mtd/spi-nor/sfdp.h > +++ b/drivers/mtd/spi-nor/sfdp.h > @@ -90,6 +90,8 @@ struct sfdp_bfpt { > #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) > #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ > > +#define BFPT_DWORD16_SOFT_RST BIT(12) > + > #define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29) > #define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29) /* Repeat */ > #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */ > -- > 2.27.0 >
Hi Tudor, On 08/07/20 04:08PM, Tudor.Ambarus@microchip.com wrote: > On 6/23/20 9:30 PM, Pratyush Yadav wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > A Soft Reset sequence will return the flash to Power-on-Reset (POR) > > state. It consists of two commands: Soft Reset Enable and Soft Reset. > > Find out if the sequence is supported from BFPT DWORD 16. > > > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > > --- > > drivers/mtd/spi-nor/core.h | 1 + > > drivers/mtd/spi-nor/sfdp.c | 4 ++++ > > drivers/mtd/spi-nor/sfdp.h | 2 ++ > > 3 files changed, 7 insertions(+) > > > > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h > > index 6338d32a0d77..79ce952c0539 100644 > > --- a/drivers/mtd/spi-nor/core.h > > +++ b/drivers/mtd/spi-nor/core.h > > @@ -26,6 +26,7 @@ enum spi_nor_option_flags { > > SNOR_F_HAS_SR_TB_BIT6 = BIT(11), > > SNOR_F_HAS_4BIT_BP = BIT(12), > > SNOR_F_HAS_SR_BP3_BIT6 = BIT(13), > > + SNOR_F_SOFT_RESET = BIT(14), > > }; > > > > struct spi_nor_read_command { > > diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c > > index 7983ff431346..8e0741d8bfd3 100644 > > --- a/drivers/mtd/spi-nor/sfdp.c > > +++ b/drivers/mtd/spi-nor/sfdp.c > > @@ -616,6 +616,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, > > break; > > } > > > > + /* Soft Reset support. */ > > + if (bfpt.dwords[BFPT_DWORD(16)] & BFPT_DWORD16_SOFT_RST) > > this can be improved. There are multiple reset methods described and you're > addressing just one of them. Yes, it can be. But xSPI only cares about the 0x66 and 0x99 reset sequence and that is what I implemented. Others can be added if they are needed in the future. In addition, I don't have hardware that supports these resets so I can't test them. IMO if someone needs other reset modes, they should send a separate patch for it. If you are worried about future work needed to support multiple soft reset modes, I can introduce a nor->soft_reset() hook that can be populated when parsing BFPT. But I think that is a bit premature. The work needed to do that is not a lot so I think we should hold off until the need really comes up. > > + nor->flags |= SNOR_F_SOFT_RESET; > > + > > /* Stop here if not JESD216 rev C or later. */ > > if (bfpt_header->length == BFPT_DWORD_MAX_JESD216B) > > return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, > > diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h > > index 6d7243067252..8ae55e98084e 100644 > > --- a/drivers/mtd/spi-nor/sfdp.h > > +++ b/drivers/mtd/spi-nor/sfdp.h > > @@ -90,6 +90,8 @@ struct sfdp_bfpt { > > #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) > > #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ > > > > +#define BFPT_DWORD16_SOFT_RST BIT(12) > > + > > #define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29) > > #define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29) /* Repeat */ > > #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 6338d32a0d77..79ce952c0539 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -26,6 +26,7 @@ enum spi_nor_option_flags { SNOR_F_HAS_SR_TB_BIT6 = BIT(11), SNOR_F_HAS_4BIT_BP = BIT(12), SNOR_F_HAS_SR_BP3_BIT6 = BIT(13), + SNOR_F_SOFT_RESET = BIT(14), }; struct spi_nor_read_command { diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c index 7983ff431346..8e0741d8bfd3 100644 --- a/drivers/mtd/spi-nor/sfdp.c +++ b/drivers/mtd/spi-nor/sfdp.c @@ -616,6 +616,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, break; } + /* Soft Reset support. */ + if (bfpt.dwords[BFPT_DWORD(16)] & BFPT_DWORD16_SOFT_RST) + nor->flags |= SNOR_F_SOFT_RESET; + /* Stop here if not JESD216 rev C or later. */ if (bfpt_header->length == BFPT_DWORD_MAX_JESD216B) return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h index 6d7243067252..8ae55e98084e 100644 --- a/drivers/mtd/spi-nor/sfdp.h +++ b/drivers/mtd/spi-nor/sfdp.h @@ -90,6 +90,8 @@ struct sfdp_bfpt { #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ +#define BFPT_DWORD16_SOFT_RST BIT(12) + #define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29) #define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29) /* Repeat */ #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */
A Soft Reset sequence will return the flash to Power-on-Reset (POR) state. It consists of two commands: Soft Reset Enable and Soft Reset. Find out if the sequence is supported from BFPT DWORD 16. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> --- drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/sfdp.c | 4 ++++ drivers/mtd/spi-nor/sfdp.h | 2 ++ 3 files changed, 7 insertions(+)