| Message ID | 20200702101331.26375-7-lars.povlsen@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | spi: Adding support for Microchip Sparx5 SoC | expand |
On Thu, Jul 02, 2020 at 12:13:29PM +0200, Lars Povlsen wrote: > The Microchip Sparx5 SPI controller has two bus segments, and use this > mux to control the bus interface mapping for any chip selects. This > decribes the bindings used to configure the mux driver. > > Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> > --- > .../mux/microchip,sparx5-spi-mux.yaml | 71 +++++++++++++++++++ > 1 file changed, 71 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml > > diff --git a/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml b/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml > new file mode 100644 > index 0000000000000..b0ce3b15a69e5 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mux/microchip,sparx5-spi-mux.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Microchip Sparx5 SPI mux > + > +maintainers: > + - Lars Povlsen <lars.povlsen@microchip.com> > + > +description: | > + The Microchip Sparx5 SPI controller has two bus segments. In order > + to switch between the appropriate bus for any given SPI slave > + (defined by a chip select), this mux driver is used. The device tree > + node for the mux will define the bus mapping for any chip > + selects. The default bus mapping for any chip select is "0", such > + that only non-default mappings need to be explicitly defined. > + > +properties: > + compatible: > + enum: > + - microchip,sparx5-spi-mux > + > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + '#mux-control-cells': > + const: 0 > + > +required: > + - compatible > + > +additionalProperties: false > + > +patternProperties: > + "^mux@[0-9a-f]$": > + type: object > + > + properties: > + reg: > + description: > + Chip select to define bus mapping for. > + minimum: 0 > + maximum: 15 > + > + microchip,bus-interface: > + description: > + The bus interface to use for this chip select. > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [0, 1] > + > + required: > + - reg > + - microchip,bus-interface > + > +examples: > + - | > + mux: mux-controller { > + compatible = "microchip,sparx5-spi-mux"; > + #address-cells = <1>; > + #size-cells = <0>; > + #mux-control-cells = <0>; How is this mux accessed? You have no control interface defined. > + mux@e { > + reg = <14>; > + microchip,bus-interface = <1>; This looks odd. I take it that there's 2 muxes for this h/w? If so then #mux-control-cells should be 1 and the cell value can be whatever you want that is meaningful for the mux controller. Could be 0,1 or perhaps 0xe if that's more useful. Rob
Rob Herring writes: > On Thu, Jul 02, 2020 at 12:13:29PM +0200, Lars Povlsen wrote: >> The Microchip Sparx5 SPI controller has two bus segments, and use this >> mux to control the bus interface mapping for any chip selects. This >> decribes the bindings used to configure the mux driver. >> >> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> >> --- >> .../mux/microchip,sparx5-spi-mux.yaml | 71 +++++++++++++++++++ >> 1 file changed, 71 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml >> >> diff --git a/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml b/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml >> new file mode 100644 >> index 0000000000000..b0ce3b15a69e5 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml >> @@ -0,0 +1,71 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/mux/microchip,sparx5-spi-mux.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Microchip Sparx5 SPI mux >> + >> +maintainers: >> + - Lars Povlsen <lars.povlsen@microchip.com> >> + >> +description: | >> + The Microchip Sparx5 SPI controller has two bus segments. In order >> + to switch between the appropriate bus for any given SPI slave >> + (defined by a chip select), this mux driver is used. The device tree >> + node for the mux will define the bus mapping for any chip >> + selects. The default bus mapping for any chip select is "0", such >> + that only non-default mappings need to be explicitly defined. >> + >> +properties: >> + compatible: >> + enum: >> + - microchip,sparx5-spi-mux >> + >> + '#address-cells': >> + const: 1 >> + >> + '#size-cells': >> + const: 0 >> + >> + '#mux-control-cells': >> + const: 0 >> + >> +required: >> + - compatible >> + >> +additionalProperties: false >> + >> +patternProperties: >> + "^mux@[0-9a-f]$": >> + type: object >> + >> + properties: >> + reg: >> + description: >> + Chip select to define bus mapping for. >> + minimum: 0 >> + maximum: 15 >> + >> + microchip,bus-interface: >> + description: >> + The bus interface to use for this chip select. >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [0, 1] >> + >> + required: >> + - reg >> + - microchip,bus-interface >> + >> +examples: >> + - | >> + mux: mux-controller { >> + compatible = "microchip,sparx5-spi-mux"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + #mux-control-cells = <0>; > > How is this mux accessed? You have no control interface defined. > >> + mux@e { >> + reg = <14>; >> + microchip,bus-interface = <1>; > > This looks odd. I take it that there's 2 muxes for this h/w? If so then > #mux-control-cells should be 1 and the cell value can be whatever you > want that is meaningful for the mux controller. Could be 0,1 or perhaps > 0xe if that's more useful. > Rob, The intended use was for the SPI driver to use mux_control_select(mux, <cs>) and then have the mux driver translate the <cs> to the right bus interface, according to its configuration. The SPI driver would have a "mux-controls" property bound to this mux. Anyway, I am getting pushed in the direction of using the "mux-mmio" and "spi-mux" combo, so this driver and bindings are being dropped again. I am currently awaiting the "rx-sample-delay-ns" issue to be clarified such that I can refresh the series. Thank you for your comments! > Rob
diff --git a/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml b/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml new file mode 100644 index 0000000000000..b0ce3b15a69e5 --- /dev/null +++ b/Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mux/microchip,sparx5-spi-mux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Sparx5 SPI mux + +maintainers: + - Lars Povlsen <lars.povlsen@microchip.com> + +description: | + The Microchip Sparx5 SPI controller has two bus segments. In order + to switch between the appropriate bus for any given SPI slave + (defined by a chip select), this mux driver is used. The device tree + node for the mux will define the bus mapping for any chip + selects. The default bus mapping for any chip select is "0", such + that only non-default mappings need to be explicitly defined. + +properties: + compatible: + enum: + - microchip,sparx5-spi-mux + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#mux-control-cells': + const: 0 + +required: + - compatible + +additionalProperties: false + +patternProperties: + "^mux@[0-9a-f]$": + type: object + + properties: + reg: + description: + Chip select to define bus mapping for. + minimum: 0 + maximum: 15 + + microchip,bus-interface: + description: + The bus interface to use for this chip select. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + required: + - reg + - microchip,bus-interface + +examples: + - | + mux: mux-controller { + compatible = "microchip,sparx5-spi-mux"; + #address-cells = <1>; + #size-cells = <0>; + #mux-control-cells = <0>; + mux@e { + reg = <14>; + microchip,bus-interface = <1>; + }; + };
The Microchip Sparx5 SPI controller has two bus segments, and use this mux to control the bus interface mapping for any chip selects. This decribes the bindings used to configure the mux driver. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> --- .../mux/microchip,sparx5-spi-mux.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/mux/microchip,sparx5-spi-mux.yaml -- 2.27.0