| Message ID | 20200716061445.628709-1-cychiang@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: qcom: sc7180: Add lpass cpu node for I2S driver | expand |
Hi, On Wed, Jul 15, 2020 at 11:14 PM Cheng-Yi Chiang <cychiang@chromium.org> wrote: > > From: Ajit Pandey <ajitp@codeaurora.org> > > Add the I2S controller node to sc7180 dtsi. > Add pinmux for pirmary and secondary I2S. s/pirmary/primary > > Signed-off-by: Ajit Pandey <ajitp@codeaurora.org> > Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org> > --- > This patch depends on these patch series so it is not ready to be merged now. > - clk: qcom: Support for Low Power Audio Clocks on SC7180 https://patchwork.kernel.org/cover/11664273/ > - arm64: dts: qcom: sc7180: Add LPASS clock controller nodes https://patchwork.kernel.org/patch/11664303/ > - ASoC: qcom: Add support for SC7180 lpass variant https://patchwork.kernel.org/cover/11650649/ Thanks for pointing out the dependencies! > arch/arm64/boot/dts/qcom/sc7180.dtsi | 132 +++++++++++++++++++++++++++ > 1 file changed, 132 insertions(+) My review is a bit rote since I don't actually know anything about audio. This is mostly just a dt-hygiene review. > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi > index 6eb14b6a47f5..2fe3bd89f950 100644 > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi > @@ -511,6 +511,34 @@ qusb2p_hstx_trim: hstx-trim-primary@25b { > }; > }; > > + lpass_cpu: lpass { Missing unit address and also sorted incorrectly. Nodes should be sorted by unit address. > + compatible = "qcom,lpass-cpu-sc7180"; Is there a pin config that generally makes sense for all boards? If so, you can add it here so it doesn't need to be added to all sub-boards. > + reg = <0 0x62F00000 0 0x29000>; nit: lower case hex for reg address, so 62f not 62F. > + reg-names = "lpass-lpaif"; > + > + iommus = <&apps_smmu 0x1020 0>; > + > + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; > + > + status = "disabled"; > + > + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, > + <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; > + > + clock-names = "noc", "audio-core", "mclk0", "sysnoc_mport", > + "pri_ibit", "sec_ibit"; > + > + #sound-dai-cells = <1>; > + > + interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>; First entry of interrupts should be GIC_SPI, which is what 0 is referring to. > + interrupt-names = "lpass-irq-lpaif"; > + }; Bindings claim you're supposed to have: #address-cells = <1>; #size-cells = <0>; Do you not need them for some reason? > sdhc_1: sdhci@7c4000 { > compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; > reg = <0 0x7c4000 0 0x1000>, > @@ -1357,6 +1385,110 @@ pinmux { > }; > }; > > + sec_mi2s_active: sec-mi2s-active { > + pinmux { > + pins = "gpio49"; > + function = "mi2s_1"; > + }; > + > + pinconf { > + pins = "gpio49"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > + > + sec_mi2s_ws_active: sec-mi2s-ws-active { > + pinmux { > + pins = "gpio50"; > + function = "mi2s_1"; > + }; > + > + pinconf { > + pins = "gpio50"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > + > + sec_mi2s_dout_active: sec-mi2s-dout-active { > + pinmux { > + pins = "gpio51"; > + function = "mi2s_1"; > + }; > + > + pinconf { > + pins = "gpio51"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > + > + pri_mi2s_active: pri-mi2s-active { > + pinmux { > + pins = "gpio53"; > + function = "mi2s_0"; > + }; > + > + pinconf { > + pins = "gpio53"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > + > + pri_mi2s_ws_active: pri-mi2s-ws-active { > + pinmux { > + pins = "gpio54"; > + function = "mi2s_0"; > + }; > + > + pinconf { > + pins = "gpio54"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > + > + pri_mi2s_dout_active: pri-mi2s-dout-active { > + pinmux { > + pins = "gpio55"; > + function = "mi2s_0"; > + }; > + > + pinconf { > + pins = "gpio55"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > + > + pri_mi2s_din_active: pri-mi2s-din-active { > + pinmux { > + pins = "gpio56"; > + function = "mi2s_0"; > + }; > + > + pinconf { > + pins = "gpio56"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; Can you group together any of the configs? See, for instance, "qup_spi0_default" where we configure 4 pins together. Then you don't need so many separate nodes to add. Also: pinconf is nearly always done in board files unless you truly have a reason to believe that it would be the same for every board. > + pri_mi2s_mclk_active: pri-mi2s-mclk-active { > + pinmux { > + pins = "gpio57"; > + function = "lpass_ext"; > + }; > + > + pinconf { > + pins = "gpio57"; > + drive-strength = <8>; > + bias-pull-up; > + }; > + }; > + > sdc1_on: sdc1-on { > pinconf-clk { > pins = "sdc1_clk"; -Doug
Hi Cheng-Yi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on linux/master linus/master v5.8-rc5 next-20200716]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Cheng-Yi-Chiang/arm64-dts-qcom-sc7180-Add-lpass-cpu-node-for-I2S-driver/20200716-141836
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r014-20200717 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project ed6b578040a85977026c93bf4188f996148f3218)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/qcom/sc7180.dtsi:521.31-32 syntax error
>> FATAL ERROR: Unable to parse input tree
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 6eb14b6a47f5..2fe3bd89f950 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -511,6 +511,34 @@ qusb2p_hstx_trim: hstx-trim-primary@25b { }; }; + lpass_cpu: lpass { + compatible = "qcom,lpass-cpu-sc7180"; + + reg = <0 0x62F00000 0 0x29000>; + reg-names = "lpass-lpaif"; + + iommus = <&apps_smmu 0x1020 0>; + + power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; + + status = "disabled"; + + clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, + <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, + <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, + <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, + <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, + <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; + + clock-names = "noc", "audio-core", "mclk0", "sysnoc_mport", + "pri_ibit", "sec_ibit"; + + #sound-dai-cells = <1>; + + interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "lpass-irq-lpaif"; + }; + sdhc_1: sdhci@7c4000 { compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; reg = <0 0x7c4000 0 0x1000>, @@ -1357,6 +1385,110 @@ pinmux { }; }; + sec_mi2s_active: sec-mi2s-active { + pinmux { + pins = "gpio49"; + function = "mi2s_1"; + }; + + pinconf { + pins = "gpio49"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + sec_mi2s_ws_active: sec-mi2s-ws-active { + pinmux { + pins = "gpio50"; + function = "mi2s_1"; + }; + + pinconf { + pins = "gpio50"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + sec_mi2s_dout_active: sec-mi2s-dout-active { + pinmux { + pins = "gpio51"; + function = "mi2s_1"; + }; + + pinconf { + pins = "gpio51"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pri_mi2s_active: pri-mi2s-active { + pinmux { + pins = "gpio53"; + function = "mi2s_0"; + }; + + pinconf { + pins = "gpio53"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pri_mi2s_ws_active: pri-mi2s-ws-active { + pinmux { + pins = "gpio54"; + function = "mi2s_0"; + }; + + pinconf { + pins = "gpio54"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pri_mi2s_dout_active: pri-mi2s-dout-active { + pinmux { + pins = "gpio55"; + function = "mi2s_0"; + }; + + pinconf { + pins = "gpio55"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pri_mi2s_din_active: pri-mi2s-din-active { + pinmux { + pins = "gpio56"; + function = "mi2s_0"; + }; + + pinconf { + pins = "gpio56"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pri_mi2s_mclk_active: pri-mi2s-mclk-active { + pinmux { + pins = "gpio57"; + function = "lpass_ext"; + }; + + pinconf { + pins = "gpio57"; + drive-strength = <8>; + bias-pull-up; + }; + }; + sdc1_on: sdc1-on { pinconf-clk { pins = "sdc1_clk";