| Message ID | 1595323468-4380-2-git-send-email-wanpengli@tencent.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] KVM: LAPIC: Prevent setting the tscdeadline timer if the lapic is hw disabled | expand |
Wanpeng Li <kernellwp@gmail.com> writes: > From: Wanpeng Li <wanpengli@tencent.com> > > Only bits 0, 1, and 3 are settable, others are reserved for APIC_TDCR. > Let's record the settable value in the virtual apic page. > > Signed-off-by: Wanpeng Li <wanpengli@tencent.com> > --- > arch/x86/kvm/lapic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index 4ce2ddd..8f7a14d 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -2068,7 +2068,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) > case APIC_TDCR: { > uint32_t old_divisor = apic->divide_count; > > - kvm_lapic_set_reg(apic, APIC_TDCR, val); > + kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb); > update_divide_count(apic); > if (apic->divide_count != old_divisor && > apic->lapic_timer.period) { AFAIU bit 2 should be 0 and other upper bits are reserved. Checking on bare hardware, # wrmsr 0x83e 0xb # rdmsr 0x83e b # wrmsr 0x83e 0xc wrmsr: CPU 0 cannot set MSR 0x0000083e to 0x000000000000000c # rdmsr 0x83e b Shouldn't we fail the write in case (val & ~0xb) ?
On Tue, 21 Jul 2020 at 18:51, Vitaly Kuznetsov <vkuznets@redhat.com> wrote: > > Wanpeng Li <kernellwp@gmail.com> writes: > > > From: Wanpeng Li <wanpengli@tencent.com> > > > > Only bits 0, 1, and 3 are settable, others are reserved for APIC_TDCR. > > Let's record the settable value in the virtual apic page. > > > > Signed-off-by: Wanpeng Li <wanpengli@tencent.com> > > --- > > arch/x86/kvm/lapic.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > > index 4ce2ddd..8f7a14d 100644 > > --- a/arch/x86/kvm/lapic.c > > +++ b/arch/x86/kvm/lapic.c > > @@ -2068,7 +2068,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) > > case APIC_TDCR: { > > uint32_t old_divisor = apic->divide_count; > > > > - kvm_lapic_set_reg(apic, APIC_TDCR, val); > > + kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb); > > update_divide_count(apic); > > if (apic->divide_count != old_divisor && > > apic->lapic_timer.period) { > > AFAIU bit 2 should be 0 and other upper bits are reserved. Checking on > bare hardware, > > # wrmsr 0x83e 0xb > # rdmsr 0x83e > b > # wrmsr 0x83e 0xc > wrmsr: CPU 0 cannot set MSR 0x0000083e to 0x000000000000000c > # rdmsr 0x83e > b > > Shouldn't we fail the write in case (val & ~0xb) ? Sorry for the late response since I just come back from vacation. I can remove the "others are reserved" in patch description for the next version. It is a little different between Intel and AMD, Intel's bit 2 is 0 and AMD is reserved. On bare-metal, Intel will refuse to set APIC_TDCR once bits except 0, 1, 3 are setting, however, AMD will accept bits 0, 1, 3 and ignore other bits setting as patch does. Before the patch, we can get back anything what we set to the APIC_TDCR, this patch improves it. Wanpeng
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 4ce2ddd..8f7a14d 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2068,7 +2068,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) case APIC_TDCR: { uint32_t old_divisor = apic->divide_count; - kvm_lapic_set_reg(apic, APIC_TDCR, val); + kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb); update_divide_count(apic); if (apic->divide_count != old_divisor && apic->lapic_timer.period) {