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[v2,0/5] Mediatek MT8192 clock support

Message ID 1596012277-8448-1-git-send-email-weiyi.lu@mediatek.com (mailing list archive)
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Series Mediatek MT8192 clock support | expand

Message

Weiyi Lu July 29, 2020, 8:44 a.m. UTC 
This series is based on v5.8-rc1

changes since v1:
- fix asymmetrical control of PLL
- have en_mask used as divider enable mask on all MediaTek SoC

Weiyi Lu (5):
  dt-bindings: ARM: Mediatek: Document bindings for MT8192
  clk: mediatek: Add dt-bindings for MT8192 clocks
  clk: mediatek: Fix asymmetrical PLL enable and disable control
  clk: mediatek: Add configurable enable control to mtk_pll_data
  clk: mediatek: Add MT8192 clock support

 .../arm/mediatek/mediatek,apmixedsys.txt      |    1 +
 .../bindings/arm/mediatek/mediatek,audsys.txt |    1 +
 .../arm/mediatek/mediatek,camsys-raw.yaml     |   40 +
 .../bindings/arm/mediatek/mediatek,camsys.txt |    1 +
 .../bindings/arm/mediatek/mediatek,imgsys.txt |    2 +
 .../arm/mediatek/mediatek,imp_iic_wrap.yaml   |   43 +
 .../arm/mediatek/mediatek,infracfg.txt        |    1 +
 .../bindings/arm/mediatek/mediatek,ipesys.txt |    1 +
 .../arm/mediatek/mediatek,mdpsys.yaml         |   38 +
 .../bindings/arm/mediatek/mediatek,mfgcfg.txt |    1 +
 .../bindings/arm/mediatek/mediatek,mmsys.txt  |    1 +
 .../bindings/arm/mediatek/mediatek,msdc.yaml  |   39 +
 .../arm/mediatek/mediatek,pericfg.yaml        |    1 +
 .../arm/mediatek/mediatek,scp-adsp.yaml       |   38 +
 .../arm/mediatek/mediatek,topckgen.txt        |    1 +
 .../arm/mediatek/mediatek,vdecsys-soc.yaml    |   38 +
 .../arm/mediatek/mediatek,vdecsys.txt         |    1 +
 .../arm/mediatek/mediatek,vencsys.txt         |    1 +
 drivers/clk/mediatek/Kconfig                  |  146 ++
 drivers/clk/mediatek/Makefile                 |   24 +
 drivers/clk/mediatek/clk-mt2701.c             |   26 +-
 drivers/clk/mediatek/clk-mt2712.c             |   30 +-
 drivers/clk/mediatek/clk-mt6765.c             |   20 +-
 drivers/clk/mediatek/clk-mt6779.c             |   24 +-
 drivers/clk/mediatek/clk-mt6797.c             |   20 +-
 drivers/clk/mediatek/clk-mt7622.c             |   18 +-
 drivers/clk/mediatek/clk-mt7629.c             |   12 +-
 drivers/clk/mediatek/clk-mt8173.c             |   42 +-
 drivers/clk/mediatek/clk-mt8183.c             |   22 +-
 drivers/clk/mediatek/clk-mt8192-aud.c         |  150 ++
 drivers/clk/mediatek/clk-mt8192-cam.c         |   69 +
 drivers/clk/mediatek/clk-mt8192-cam_rawa.c    |   56 +
 drivers/clk/mediatek/clk-mt8192-cam_rawb.c    |   56 +
 drivers/clk/mediatek/clk-mt8192-cam_rawc.c    |   56 +
 drivers/clk/mediatek/clk-mt8192-img.c         |   57 +
 drivers/clk/mediatek/clk-mt8192-img2.c        |   59 +
 .../clk/mediatek/clk-mt8192-imp_iic_wrap_c.c  |   61 +
 .../clk/mediatek/clk-mt8192-imp_iic_wrap_e.c  |   55 +
 .../clk/mediatek/clk-mt8192-imp_iic_wrap_n.c  |   57 +
 .../clk/mediatek/clk-mt8192-imp_iic_wrap_s.c  |   59 +
 .../clk/mediatek/clk-mt8192-imp_iic_wrap_w.c  |   55 +
 .../clk/mediatek/clk-mt8192-imp_iic_wrap_ws.c |   59 +
 drivers/clk/mediatek/clk-mt8192-ipe.c         |   61 +
 drivers/clk/mediatek/clk-mt8192-mdp.c         |   89 +
 drivers/clk/mediatek/clk-mt8192-mfg.c         |   54 +
 drivers/clk/mediatek/clk-mt8192-mm.c          |  108 ++
 drivers/clk/mediatek/clk-mt8192-msdc.c        |   54 +
 drivers/clk/mediatek/clk-mt8192-msdc_top.c    |   83 +
 drivers/clk/mediatek/clk-mt8192-scp_adsp.c    |   55 +
 drivers/clk/mediatek/clk-mt8192-vdec.c        |   81 +
 drivers/clk/mediatek/clk-mt8192-vdec_soc.c    |   86 +
 drivers/clk/mediatek/clk-mt8192-venc.c        |   57 +
 drivers/clk/mediatek/clk-mt8192.c             | 1549 +++++++++++++++++
 drivers/clk/mediatek/clk-mtk.h                |    2 +
 drivers/clk/mediatek/clk-mux.h                |   15 +
 drivers/clk/mediatek/clk-pll.c                |   20 +-
 include/dt-bindings/clock/mt8192-clk.h        |  593 +++++++
 57 files changed, 4284 insertions(+), 105 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys-raw.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mdpsys.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,msdc.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,scp-adsp.yaml
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml
 create mode 100644 drivers/clk/mediatek/clk-mt8192-aud.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-cam.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawa.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawb.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-cam_rawc.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-img.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-img2.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_c.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_e.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_n.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_s.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_w.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap_ws.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-ipe.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-mdp.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-mfg.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-mm.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-msdc.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-msdc_top.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-scp_adsp.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-vdec_soc.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192-venc.c
 create mode 100644 drivers/clk/mediatek/clk-mt8192.c
 create mode 100644 include/dt-bindings/clock/mt8192-clk.h

Comments

Enric Balletbo Serra July 29, 2020, 9:32 a.m. UTC | #1 
Hi Weiyi,

Thank you for your patch. Some few comment below, I'll focus on
clk-mt8192-mm file, but I think can apply to other files too.

[snip]

> diff --git a/drivers/clk/mediatek/clk-mt8192-mm.c b/drivers/clk/mediatek/clk-mt8192-mm.c
> new file mode 100644
> index 0000000..02eef24
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8192-mm.c
> @@ -0,0 +1,108 @@
> +// SPDX-License-Identifier: GPL-2.0

nit: Although is a valid license identifier for the kernel would be
better to use the non-deprecated form by SPDX, GPL-2.0-only

> +//
> +// Copyright (c) 2020 MediaTek Inc.
> +// Author: Weiyi Lu <weiyi.lu@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
> +
> +#include <dt-bindings/clock/mt8192-clk.h>
> +
> +static const struct mtk_gate_regs mm0_cg_regs = {
> +       .set_ofs = 0x104,
> +       .clr_ofs = 0x108,
> +       .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs mm1_cg_regs = {
> +       .set_ofs = 0x114,
> +       .clr_ofs = 0x118,
> +       .sta_ofs = 0x110,
> +};
> +
> +static const struct mtk_gate_regs mm2_cg_regs = {
> +       .set_ofs = 0x1a4,
> +       .clr_ofs = 0x1a8,
> +       .sta_ofs = 0x1a0,
> +};
> +
> +#define GATE_MM0(_id, _name, _parent, _shift)                  \
> +       GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift,     \
> +               &mtk_clk_gate_ops_setclr)

nit: You can take advantage of the new line length limit, which is now
100 characters.

> +
> +#define GATE_MM1(_id, _name, _parent, _shift)                  \
> +       GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift,     \
> +               &mtk_clk_gate_ops_setclr)
> +

ditto

> +#define GATE_MM2(_id, _name, _parent, _shift)                  \
> +       GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift,     \
> +               &mtk_clk_gate_ops_setclr)
> +

ditto

> +static const struct mtk_gate mm_clks[] = {
> +       /* MM0 */
> +       GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp_sel", 0),
> +       GATE_MM0(CLK_MM_DISP_CONFIG, "mm_disp_config", "disp_sel", 1),
> +       GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "disp_sel", 2),
> +       GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 3),
> +       GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "disp_sel", 4),
> +       GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp_sel", 5),
> +       GATE_MM0(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0", "disp_sel", 6),
> +       GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "disp_sel", 7),
> +       GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp_sel", 8),
> +       GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp_sel", 9),
> +       GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp_sel", 10),
> +       GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra", "disp_sel", 11),
> +       GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp_sel", 12),
> +       GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp_sel", 13),
> +       GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "disp_sel", 14),
> +       GATE_MM0(CLK_MM_DSI0, "mm_dsi0", "disp_sel", 15),
> +       GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp_sel", 16),
> +       GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "disp_sel", 17),
> +       GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp_sel", 18),
> +       GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "disp_sel", 19),
> +       GATE_MM0(CLK_MM_MDP_TDSHP4, "mm_mdp_tdshp4", "disp_sel", 20),
> +       GATE_MM0(CLK_MM_MDP_RSZ4, "mm_mdp_rsz4", "disp_sel", 21),
> +       GATE_MM0(CLK_MM_MDP_AAL4, "mm_mdp_aal4", "disp_sel", 22),
> +       GATE_MM0(CLK_MM_MDP_HDR4, "mm_mdp_hdr4", "disp_sel", 23),
> +       GATE_MM0(CLK_MM_MDP_RDMA4, "mm_mdp_rdma4", "disp_sel", 24),
> +       GATE_MM0(CLK_MM_MDP_COLOR4, "mm_mdp_color4", "disp_sel", 25),
> +       GATE_MM0(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp_sel", 26),
> +       GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals", "disp_sel", 27),
> +       GATE_MM0(CLK_MM_DISP_OVL2_2L, "mm_disp_ovl2_2l", "disp_sel", 28),
> +       GATE_MM0(CLK_MM_DISP_RDMA4, "mm_disp_rdma4", "disp_sel", 29),
> +       GATE_MM0(CLK_MM_DISP_DPI0, "mm_disp_dpi0", "disp_sel", 30),
> +       /* MM1 */
> +       GATE_MM1(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "disp_sel", 0),
> +       /* MM2 */
> +       GATE_MM2(CLK_MM_DSI_DSI0, "mm_dsi_dsi0", "disp_sel", 0),
> +       GATE_MM2(CLK_MM_DPI_DPI0, "mm_dpi_dpi0", "dpi_sel", 8),
> +       GATE_MM2(CLK_MM_26MHZ, "mm_26mhz", "clk26m", 24),
> +       GATE_MM2(CLK_MM_32KHZ, "mm_32khz", "clk32k", 25),
> +};
> +
> +static int clk_mt8192_mm_probe(struct platform_device *pdev)
> +{
> +       struct device *dev = &pdev->dev;
> +       struct device_node *node = dev->parent->of_node;
> +       struct clk_onecell_data *clk_data;
> +
> +       clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);

mtk_alloc_clk_data can return NULL

           if (!clk_data)
              return -ENOMEM;

> +
> +       mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
> +                       clk_data);
> +

The above function can fail, better check for error

         if (ret)
             return ret;

> +       return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +

No need for double line spacing.

> +static struct platform_driver clk_mt8192_mm_drv = {
> +       .probe = clk_mt8192_mm_probe,
> +       .driver = {
> +               .name = "clk-mt8192-mm",
> +       },
> +};
> +
> +builtin_platform_driver(clk_mt8192_mm_drv);

[snip]
Weiyi Lu Aug. 11, 2020, 7:03 a.m. UTC | #2 
On Wed, 2020-07-29 at 11:32 +0200, Enric Balletbo Serra wrote:
> Hi Weiyi,
> 
> Thank you for your patch. Some few comment below, I'll focus on
> clk-mt8192-mm file, but I think can apply to other files too.
> 
> [snip]
> 
> > diff --git a/drivers/clk/mediatek/clk-mt8192-mm.c b/drivers/clk/mediatek/clk-mt8192-mm.c
> > new file mode 100644
> > index 0000000..02eef24
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8192-mm.c
> > @@ -0,0 +1,108 @@
> > +// SPDX-License-Identifier: GPL-2.0
> 
> nit: Although is a valid license identifier for the kernel would be
> better to use the non-deprecated form by SPDX, GPL-2.0-only
> 
> > +//
> > +// Copyright (c) 2020 MediaTek Inc.
> > +// Author: Weiyi Lu <weiyi.lu@mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include <dt-bindings/clock/mt8192-clk.h>
> > +
> > +static const struct mtk_gate_regs mm0_cg_regs = {
> > +       .set_ofs = 0x104,
> > +       .clr_ofs = 0x108,
> > +       .sta_ofs = 0x100,
> > +};
> > +
> > +static const struct mtk_gate_regs mm1_cg_regs = {
> > +       .set_ofs = 0x114,
> > +       .clr_ofs = 0x118,
> > +       .sta_ofs = 0x110,
> > +};
> > +
> > +static const struct mtk_gate_regs mm2_cg_regs = {
> > +       .set_ofs = 0x1a4,
> > +       .clr_ofs = 0x1a8,
> > +       .sta_ofs = 0x1a0,
> > +};
> > +
> > +#define GATE_MM0(_id, _name, _parent, _shift)                  \
> > +       GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift,     \
> > +               &mtk_clk_gate_ops_setclr)
> 
> nit: You can take advantage of the new line length limit, which is now
> 100 characters.
> 

OK, thanks for reminding.

> > +
> > +#define GATE_MM1(_id, _name, _parent, _shift)                  \
> > +       GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift,     \
> > +               &mtk_clk_gate_ops_setclr)
> > +
> 
> ditto
> 

Got it.

> > +#define GATE_MM2(_id, _name, _parent, _shift)                  \
> > +       GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift,     \
> > +               &mtk_clk_gate_ops_setclr)
> > +
> 
> ditto
> 
> > +static const struct mtk_gate mm_clks[] = {
> > +       /* MM0 */
> > +       GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp_sel", 0),
> > +       GATE_MM0(CLK_MM_DISP_CONFIG, "mm_disp_config", "disp_sel", 1),
> > +       GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "disp_sel", 2),
> > +       GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp_sel", 3),
> > +       GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "disp_sel", 4),
> > +       GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp_sel", 5),
> > +       GATE_MM0(CLK_MM_DISP_UFBC_WDMA0, "mm_disp_ufbc_wdma0", "disp_sel", 6),
> > +       GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "disp_sel", 7),
> > +       GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp_sel", 8),
> > +       GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp_sel", 9),
> > +       GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp_sel", 10),
> > +       GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra", "disp_sel", 11),
> > +       GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp_sel", 12),
> > +       GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "disp_sel", 13),
> > +       GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "disp_sel", 14),
> > +       GATE_MM0(CLK_MM_DSI0, "mm_dsi0", "disp_sel", 15),
> > +       GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp_sel", 16),
> > +       GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "disp_sel", 17),
> > +       GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp_sel", 18),
> > +       GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "disp_sel", 19),
> > +       GATE_MM0(CLK_MM_MDP_TDSHP4, "mm_mdp_tdshp4", "disp_sel", 20),
> > +       GATE_MM0(CLK_MM_MDP_RSZ4, "mm_mdp_rsz4", "disp_sel", 21),
> > +       GATE_MM0(CLK_MM_MDP_AAL4, "mm_mdp_aal4", "disp_sel", 22),
> > +       GATE_MM0(CLK_MM_MDP_HDR4, "mm_mdp_hdr4", "disp_sel", 23),
> > +       GATE_MM0(CLK_MM_MDP_RDMA4, "mm_mdp_rdma4", "disp_sel", 24),
> > +       GATE_MM0(CLK_MM_MDP_COLOR4, "mm_mdp_color4", "disp_sel", 25),
> > +       GATE_MM0(CLK_MM_DISP_Y2R0, "mm_disp_y2r0", "disp_sel", 26),
> > +       GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals", "disp_sel", 27),
> > +       GATE_MM0(CLK_MM_DISP_OVL2_2L, "mm_disp_ovl2_2l", "disp_sel", 28),
> > +       GATE_MM0(CLK_MM_DISP_RDMA4, "mm_disp_rdma4", "disp_sel", 29),
> > +       GATE_MM0(CLK_MM_DISP_DPI0, "mm_disp_dpi0", "disp_sel", 30),
> > +       /* MM1 */
> > +       GATE_MM1(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "disp_sel", 0),
> > +       /* MM2 */
> > +       GATE_MM2(CLK_MM_DSI_DSI0, "mm_dsi_dsi0", "disp_sel", 0),
> > +       GATE_MM2(CLK_MM_DPI_DPI0, "mm_dpi_dpi0", "dpi_sel", 8),
> > +       GATE_MM2(CLK_MM_26MHZ, "mm_26mhz", "clk26m", 24),
> > +       GATE_MM2(CLK_MM_32KHZ, "mm_32khz", "clk32k", 25),
> > +};
> > +
> > +static int clk_mt8192_mm_probe(struct platform_device *pdev)
> > +{
> > +       struct device *dev = &pdev->dev;
> > +       struct device_node *node = dev->parent->of_node;
> > +       struct clk_onecell_data *clk_data;
> > +
> > +       clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
> 
> mtk_alloc_clk_data can return NULL
> 
>            if (!clk_data)
>               return -ENOMEM;
> 
> > +
> > +       mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
> > +                       clk_data);
> > +
> 
> The above function can fail, better check for error
> 
>          if (ret)
>              return ret;
> 

OK, I'll fix in next version.

> > +       return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > +}
> > +
> > +
> 
> No need for double line spacing.
> 

Got it.

> > +static struct platform_driver clk_mt8192_mm_drv = {
> > +       .probe = clk_mt8192_mm_probe,
> > +       .driver = {
> > +               .name = "clk-mt8192-mm",
> > +       },
> > +};
> > +
> > +builtin_platform_driver(clk_mt8192_mm_drv);
> 
> [snip]
> 
> _______________________________________________
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