| Message ID | 20200717133753.127282-9-hdegoede@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | acpi/pwm/i915: Convert pwm-crc and i915 driver's PWM code to use the atomic PWM API | expand |
On Fri, Jul 17, 2020 at 03:37:45PM +0200, Hans de Goede wrote: > The CRC PWM controller has a clock-divider which divides the clock with > a value between 1-128. But as can seen from the PWM_DIV_CLK_xxx > defines, this range maps to a register value of 0-127. > > So after calculating the clock-divider we must subtract 1 to get the > register value, unless the requested frequency was so high that the > calculation has already resulted in a (rounded) divider value of 0. > > Note that before this fix, setting a period of PWM_MAX_PERIOD_NS which > corresponds to the max. divider value of 128 could have resulted in a > bug where the code would use 128 as divider-register value which would > have resulted in an actual divider value of 0 (and the enable bit being > set). A rounding error stopped this bug from actually happen. This > same rounding error means that after the subtraction of 1 it is impossible > to set the divider to 128. Also bump PWM_MAX_PERIOD_NS by 1 ns to allow > setting a divider of 128 (register-value 127). Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > --- > Changes in v3: > - Introduce crc_pwm_calc_clk_div() here instead of later in the patch-set > to reduce the amount of churn in the patch-set a bit > --- > drivers/pwm/pwm-crc.c | 17 ++++++++++++++--- > 1 file changed, 14 insertions(+), 3 deletions(-) > > diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c > index c056eb9b858c..44ec7d5b63e1 100644 > --- a/drivers/pwm/pwm-crc.c > +++ b/drivers/pwm/pwm-crc.c > @@ -22,7 +22,7 @@ > #define PWM_MAX_LEVEL 0xFF > > #define PWM_BASE_CLK_MHZ 6 /* 6 MHz */ > -#define PWM_MAX_PERIOD_NS 5461333 /* 183 Hz */ > +#define PWM_MAX_PERIOD_NS 5461334 /* 183 Hz */ > > /** > * struct crystalcove_pwm - Crystal Cove PWM controller > @@ -39,6 +39,18 @@ static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc) > return container_of(pc, struct crystalcove_pwm, chip); > } > > +static int crc_pwm_calc_clk_div(int period_ns) > +{ > + int clk_div; > + > + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC); > + /* clk_div 1 - 128, maps to register values 0-127 */ > + if (clk_div > 0) > + clk_div--; > + > + return clk_div; > +} > + > static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) > { > struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); > @@ -68,11 +80,10 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, > } > > if (pwm_get_period(pwm) != period_ns) { > - int clk_div; > + int clk_div = crc_pwm_calc_clk_div(period_ns); > > /* changing the clk divisor, need to disable fisrt */ > crc_pwm_disable(c, pwm); > - clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC); > > regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, > clk_div | PWM_OUTPUT_ENABLE); > -- > 2.26.2 >
diff --git a/drivers/pwm/pwm-crc.c b/drivers/pwm/pwm-crc.c index c056eb9b858c..44ec7d5b63e1 100644 --- a/drivers/pwm/pwm-crc.c +++ b/drivers/pwm/pwm-crc.c @@ -22,7 +22,7 @@ #define PWM_MAX_LEVEL 0xFF #define PWM_BASE_CLK_MHZ 6 /* 6 MHz */ -#define PWM_MAX_PERIOD_NS 5461333 /* 183 Hz */ +#define PWM_MAX_PERIOD_NS 5461334 /* 183 Hz */ /** * struct crystalcove_pwm - Crystal Cove PWM controller @@ -39,6 +39,18 @@ static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc) return container_of(pc, struct crystalcove_pwm, chip); } +static int crc_pwm_calc_clk_div(int period_ns) +{ + int clk_div; + + clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC); + /* clk_div 1 - 128, maps to register values 0-127 */ + if (clk_div > 0) + clk_div--; + + return clk_div; +} + static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm) { struct crystalcove_pwm *crc_pwm = to_crc_pwm(c); @@ -68,11 +80,10 @@ static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm, } if (pwm_get_period(pwm) != period_ns) { - int clk_div; + int clk_div = crc_pwm_calc_clk_div(period_ns); /* changing the clk divisor, need to disable fisrt */ crc_pwm_disable(c, pwm); - clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC); regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, clk_div | PWM_OUTPUT_ENABLE);
The CRC PWM controller has a clock-divider which divides the clock with a value between 1-128. But as can seen from the PWM_DIV_CLK_xxx defines, this range maps to a register value of 0-127. So after calculating the clock-divider we must subtract 1 to get the register value, unless the requested frequency was so high that the calculation has already resulted in a (rounded) divider value of 0. Note that before this fix, setting a period of PWM_MAX_PERIOD_NS which corresponds to the max. divider value of 128 could have resulted in a bug where the code would use 128 as divider-register value which would have resulted in an actual divider value of 0 (and the enable bit being set). A rounding error stopped this bug from actually happen. This same rounding error means that after the subtraction of 1 it is impossible to set the divider to 128. Also bump PWM_MAX_PERIOD_NS by 1 ns to allow setting a divider of 128 (register-value 127). Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- Changes in v3: - Introduce crc_pwm_calc_clk_div() here instead of later in the patch-set to reduce the amount of churn in the patch-set a bit --- drivers/pwm/pwm-crc.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-)