[RFC,v2,58/76] target/riscv: rvv-0.9: slide instructions

Message ID	20200722091641.8834-59-frank.chang@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=6956=BB=nongnu.org=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2AE4820787 From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 58/76] target/riscv: rvv-0.9: slide instructions Date: Wed, 22 Jul 2020 17:16:21 +0800 Message-Id: <20200722091641.8834-59-frank.chang@sifive.com> In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1031.google.com Precedence: list Cc: Frank Chang <frank.chang@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	target/riscv: support vector extension v0.9 \| expand [RFC,v2,00/76] target/riscv: support vector extension v0.9 [RFC,v2,01/76] target/riscv: drop vector 0.7.1 support [RFC,v2,02/76] target/riscv: rvv-0.9: support vector 0.9 [RFC,v2,03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion [RFC,v2,04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() [RFC,v2,05/76] target/riscv: fix return value of do_opivx_widen() [RFC,v2,06/76] target/riscv: fix vill bit index in vtype register [RFC,v2,07/76] target/riscv: Use FIELD_EX32() to extract wd field [RFC,v2,08/76] target/riscv: rvv-0.9: add mstatus VS field [RFC,v2,09/76] target/riscv: rvv-0.9: add sstatus VS field [RFC,v2,10/76] target/riscv: rvv-0.9: add translation-time vector context status [RFC,v2,11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register [RFC,v2,12/76] target/riscv: rvv-0.9: add vcsr register [RFC,v2,13/76] target/riscv: rvv-0.9: add vlenb register [RFC,v2,14/76] target/riscv: rvv-0.9: remove MLEN calculations [RFC,v2,15/76] target/riscv: rvv-0.9: add fractional LMUL [RFC,v2,16/76] target/riscv: rvv-0.9: add VMA and VTA [RFC,v2,17/76] target/riscv: rvv-0.9: update check functions [RFC,v2,18/76] target/riscv: introduce more imm value modes in translator functions [RFC,v2,19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper [RFC,v2,20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans [RFC,v2,21/76] target/riscv: rvv-0.9: configure instructions [RFC,v2,22/76] target/riscv: rvv-0.9: stride load and store instructions [RFC,v2,23/76] target/riscv: rvv-0.9: index load and store instructions [RFC,v2,24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns [RFC,v2,25/76] target/riscv: rvv-0.9: fault-only-first unit stride load [RFC,v2,26/76] target/riscv: rvv-0.9: amo operations [RFC,v2,27/76] target/riscv: rvv-0.9: load/store whole register instructions [RFC,v2,28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns [RFC,v2,29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation [RFC,v2,30/76] target/riscv: rvv-0.9: floating-point square-root instruction [RFC,v2,31/76] target/riscv: rvv-0.9: floating-point classify instructions [RFC,v2,32/76] target/riscv: rvv-0.9: mask population count instruction [RFC,v2,33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction [RFC,v2,34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions [RFC,v2,35/76] target/riscv: rvv-0.9: iota instruction [RFC,v2,36/76] target/riscv: rvv-0.9: element index instruction [RFC,v2,37/76] target/riscv: rvv-0.9: allow load element with sign-extended [RFC,v2,38/76] target/riscv: rvv-0.9: register gather instructions [RFC,v2,39/76] target/riscv: rvv-0.9: integer scalar move instructions [RFC,v2,40/76] target/riscv: rvv-0.9: floating-point move instruction [RFC,v2,41/76] target/riscv: rvv-0.9: floating-point scalar move instructions [RFC,v2,42/76] target/riscv: rvv-0.9: whole register move instructions [RFC,v2,43/76] target/riscv: rvv-0.9: integer extension instructions [RFC,v2,44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions [RFC,v2,45/76] target/riscv: rvv-0.9: single-width bit shift instructions [RFC,v2,46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow [RFC,v2,47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions [RFC,v2,48/76] target/riscv: rvv-0.9: widening integer multiply-add instructions [RFC,v2,49/76] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions [RFC,v2,50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions [RFC,v2,51/76] target/riscv: rvv-0.9: integer comparison instructions [RFC,v2,52/76] fpu: implement full set compare for fp16 [RFC,v2,53/76] target/riscv: use softfloat lib float16 comparison functions [RFC,v2,54/76] target/riscv: rvv-0.9: floating-point compare instructions [RFC,v2,55/76] target/riscv: rvv-0.9: single-width integer reduction instructions [RFC,v2,56/76] target/riscv: rvv-0.9: widening integer reduction instructions [RFC,v2,57/76] target/riscv: rvv-0.9: mask-register logical instructions [RFC,v2,58/76] target/riscv: rvv-0.9: slide instructions [RFC,v2,59/76] target/riscv: rvv-0.9: floating-point slide instructions [RFC,v2,60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions [RFC,v2,61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions [RFC,v2,62/76] target/riscv: rvv-0.9: single-width floating-point reduction [RFC,v2,63/76] target/riscv: rvv-0.9: widening floating-point reduction instructions [RFC,v2,64/76] target/riscv: rvv-0.9: single-width scaling shift instructions [RFC,v2,65/76] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add [RFC,v2,66/76] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf [RFC,v2,67/76] target/riscv: rvv-0.9: remove integer extract instruction [RFC,v2,68/76] fpu: add api to handle alternative sNaN propagation [RFC,v2,69/76] target/riscv: rvv-0.9: floating-point min/max instructions [RFC,v2,70/76] softfloat: add fp16 and uint8/int8 interconvert functions [RFC,v2,71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert [RFC,v2,72/76] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert [RFC,v2,73/76] fpu: fix float16 nan check [RFC,v2,74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map [RFC,v2,75/76] target/riscv: gdb: support vector registers for rv64 [RFC,v2,76/76] target/riscv: gdb: support vector registers for rv32

Message ID

20200722091641.8834-59-frank.chang@sifive.com (mailing list archive)

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New, archived

Headers

DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2AE4820787
From: frank.chang@sifive.com
To: qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Subject: [RFC v2 58/76] target/riscv: rvv-0.9: slide instructions
Date: Wed, 22 Jul 2020 17:16:21 +0800
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Series

target/riscv: support vector extension v0.9 | expand

Commit Message

Frank Chang July 22, 2020, 9:16 a.m. UTC

From: Frank Chang <frank.chang@sifive.com>

* Fix offset overflow issue.
* Remove clear function from helper functions as the tail elements
  are unchanged in RVV 0.9.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/vector_helper.c | 83 ++++++++++++++++--------------------
 1 file changed, 37 insertions(+), 46 deletions(-)

Comments

Richard Henderson July 31, 2020, 3:57 p.m. UTC | #1

On 7/22/20 2:16 AM, frank.chang@sifive.com wrote:
> -#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H, CLEAR_FN)                  \
> +#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H)                            \
>  void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
>                    CPURISCVState *env, uint32_t desc)                      \
>  {                                                                         \
> -    uint32_t vlmax = env_archcpu(env)->cfg.vlen;                          \
> +    uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);          \
>      uint32_t vm = vext_vm(desc);                                          \
> -    uint32_t vta = vext_vta(desc);                                        \
>      uint32_t vl = env->vl;                                                \
>      target_ulong offset = s1, i;                                          \
>                                                                            \
>      for (i = 0; i < vl; ++i) {                                            \
> +        /* offset may be a large value, which j may overflow */           \
>          target_ulong j = i + offset;                                      \
> +        bool is_valid = (offset >= vlmax || j >= vlmax) ? false : true;   \

This is... silly verbose.
But also, the test is partially loop invariant and entirely predictable,
allowing loop fission.

>          if (!vm && !vext_elem_mask(v0, i)) {                              \
>              continue;                                                     \
>          }                                                                 \
> -        *((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j));  \
> +        *((ETYPE *)vd + H(i)) = is_valid ? *((ETYPE *)vs2 + H(j)) : 0;  \
>      }                                                                     \
> -    CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE));     \
>  }

E.g.

    i_max = s1 < vlmax ? vlmax - s1 : 0;
    for (i = 0; i < i_max; ++i) {
        if (vext_elem_mask(v0, i)) {
            *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + s1));
        }
    }
    for (i = i_max; i < vl; ++i) {
        if (vext_elem_mask(v0, i)) {
            *((ETYPE *)vd + H(i)) = 0;
        }
    }


r~

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index bb426e224c..b47ca6c406 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4923,64 +4923,59 @@  GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq)
  */
 
 /* Vector Slide Instructions */
-#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H, CLEAR_FN)                    \
-void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
-                  CPURISCVState *env, uint32_t desc)                      \
-{                                                                         \
-    uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);          \
-    uint32_t vm = vext_vm(desc);                                          \
-    uint32_t vta = vext_vta(desc);                                        \
-    uint32_t vl = env->vl;                                                \
-    target_ulong offset = s1, i;                                          \
-                                                                          \
-    for (i = offset; i < vl; i++) {                                       \
-        if (!vm && !vext_elem_mask(v0, i)) {                              \
-            continue;                                                     \
-        }                                                                 \
-        *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset));          \
-    }                                                                     \
-    CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE));     \
+#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H)                      \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
+                  CPURISCVState *env, uint32_t desc)              \
+{                                                                 \
+    uint32_t vm = vext_vm(desc);                                  \
+    uint32_t vl = env->vl;                                        \
+    target_ulong offset = s1, i;                                  \
+                                                                  \
+    for (i = offset; i < vl; i++) {                               \
+        if (!vm && !vext_elem_mask(v0, i)) {                      \
+            continue;                                             \
+        }                                                         \
+        *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset));  \
+    }                                                             \
 }
 
 /* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t,  H1)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8)
 
-#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H, CLEAR_FN)                  \
+#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H)                            \
 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
                   CPURISCVState *env, uint32_t desc)                      \
 {                                                                         \
-    uint32_t vlmax = env_archcpu(env)->cfg.vlen;                          \
+    uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);          \
     uint32_t vm = vext_vm(desc);                                          \
-    uint32_t vta = vext_vta(desc);                                        \
     uint32_t vl = env->vl;                                                \
     target_ulong offset = s1, i;                                          \
                                                                           \
     for (i = 0; i < vl; ++i) {                                            \
+        /* offset may be a large value, which j may overflow */           \
         target_ulong j = i + offset;                                      \
+        bool is_valid = (offset >= vlmax || j >= vlmax) ? false : true;   \
         if (!vm && !vext_elem_mask(v0, i)) {                              \
             continue;                                                     \
         }                                                                 \
-        *((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j));  \
+        *((ETYPE *)vd + H(i)) = is_valid ? *((ETYPE *)vs2 + H(j)) : 0;  \
     }                                                                     \
-    CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE));     \
 }
 
 /* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t,  H1)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
 
-#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H, CLEAR_FN)                   \
+#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H)                             \
 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
                   CPURISCVState *env, uint32_t desc)                      \
 {                                                                         \
-    uint32_t vlmax = env_archcpu(env)->cfg.vlen;                          \
     uint32_t vm = vext_vm(desc);                                          \
-    uint32_t vta = vext_vta(desc);                                        \
     uint32_t vl = env->vl;                                                \
     uint32_t i;                                                           \
                                                                           \
@@ -4994,22 +4989,19 @@  void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
             *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1));           \
         }                                                                 \
     }                                                                     \
-    CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE));     \
 }
 
 /* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t,  H1)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8)
 
-#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H, CLEAR_FN)                 \
+#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H)                           \
 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
                   CPURISCVState *env, uint32_t desc)                      \
 {                                                                         \
-    uint32_t vlmax = env_archcpu(env)->cfg.vlen;                          \
     uint32_t vm = vext_vm(desc);                                          \
-    uint32_t vta = vext_vta(desc);                                        \
     uint32_t vl = env->vl;                                                \
     uint32_t i;                                                           \
                                                                           \
@@ -5023,14 +5015,13 @@  void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
             *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1));           \
         }                                                                 \
     }                                                                     \
-    CLEAR_FN(vd, vta, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE));     \
 }
 
 /* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1, clearb)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2, clearh)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4, clearl)
-GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t,  H1)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8)
 
 /* Vector Register Gather Instruction */
 #define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H, CLEAR_FN)                    \

[RFC,v2,58/76] target/riscv: rvv-0.9: slide instructions

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