| Message ID | 20200810092208.27320-3-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | r8a774e1 add FCPF, FCPV and VSP nodes | expand |
Hi Prabhakar, On Mon, Aug 10, 2020 at 11:22 AM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > The RZ/G2H (R8A774E1) has 6 VSP instances. > > Based on the work done for r8a7795 SoC. > > Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > @@ -2374,6 +2374,72 @@ > status = "disabled"; > }; > > + vspbc: vsp@fe920000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xfe920000 0 0x8000>; > + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 624>; > + power-domains = <&sysc R8A774E1_PD_A3VP>; > + resets = <&cpg 624>; > + > + renesas,fcp = <&fcpvb1>; > + }; > + > + vspbd: vsp@fe960000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xfe960000 0 0x8000>; > + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 626>; > + power-domains = <&sysc R8A774E1_PD_A3VP>; > + resets = <&cpg 626>; > + > + renesas,fcp = <&fcpvb1>; According to "FCPVB0 (for VSPBD): H' FE96_F000", this should be renesas,fcp = <&fcpvb0>; ? If you agree, I can fix that while applying. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.10. Gr{oetje,eeting}s, Geert
Hi Geert, Thank you for the review. On Mon, Aug 10, 2020 at 11:29 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > Hi Prabhakar, > > On Mon, Aug 10, 2020 at 11:22 AM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > > From: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > > > The RZ/G2H (R8A774E1) has 6 VSP instances. > > > > Based on the work done for r8a7795 SoC. > > > > Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Thanks for your patch! > > > --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi > > @@ -2374,6 +2374,72 @@ > > status = "disabled"; > > }; > > > > + vspbc: vsp@fe920000 { > > + compatible = "renesas,vsp2"; > > + reg = <0 0xfe920000 0 0x8000>; > > + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&cpg CPG_MOD 624>; > > + power-domains = <&sysc R8A774E1_PD_A3VP>; > > + resets = <&cpg 624>; > > + > > + renesas,fcp = <&fcpvb1>; > > + }; > > + > > + vspbd: vsp@fe960000 { > > + compatible = "renesas,vsp2"; > > + reg = <0 0xfe960000 0 0x8000>; > > + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&cpg CPG_MOD 626>; > > + power-domains = <&sysc R8A774E1_PD_A3VP>; > > + resets = <&cpg 626>; > > + > > + renesas,fcp = <&fcpvb1>; > > According to "FCPVB0 (for VSPBD): H' FE96_F000", this should be > > renesas,fcp = <&fcpvb0>; > > ? If you agree, I can fix that while applying. > Agreed should be fcpvb0, thank you for taking care of it. Cheers, Prabhakar > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > i.e. will queue in renesas-devel for v5.10. > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 1954a07f3e85..8f762bd2c9aa 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2374,6 +2374,72 @@ status = "disabled"; }; + vspbc: vsp@fe920000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 624>; + + renesas,fcp = <&fcpvb1>; + }; + + vspbd: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb1>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + + vspi1: vsp@fe9b0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9b0000 0 0x8000>; + interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 630>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + resets = <&cpg 630>; + + renesas,fcp = <&fcpvi1>; + }; + fcpf0: fcp@fe950000 { compatible = "renesas,fcpf"; reg = <0 0xfe950000 0 0x200>;