| Message ID | 1596713672-8146-2-git-send-email-sjakhade@cadence.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm: Add support for Cadence MHDP DPI/DP bridge and J721E wrapper. | expand |
Hi Swapnil, Thank you for the patch. On Thu, Aug 06, 2020 at 01:34:30PM +0200, Swapnil Jakhade wrote: > From: Yuti Amonkar <yamonkar@cadence.com> > > Document the bindings used for the Cadence MHDP DPI/DP bridge in > yaml format. > > Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> > Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> > Reviewed-by: Rob Herring <robh@kernel.org> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > .../bindings/display/bridge/cdns,mhdp.yaml | 139 ++++++++++++++++++ > 1 file changed, 139 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > > diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > new file mode 100644 > index 000000000000..dabccefe0983 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml > @@ -0,0 +1,139 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Cadence MHDP bridge > + > +maintainers: > + - Swapnil Jakhade <sjakhade@cadence.com> > + - Yuti Amonkar <yamonkar@cadence.com> > + > +properties: > + compatible: > + enum: > + - cdns,mhdp8546 > + - ti,j721e-mhdp8546 > + > + reg: > + minItems: 1 > + maxItems: 2 > + items: > + - description: > + Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P). > + The AUX and PMA registers are not part of this range, they are instead > + included in the associated PHY. > + - description: > + Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. > + > + reg-names: > + minItems: 1 > + maxItems: 2 > + items: > + - const: mhdptx > + - const: j721e-intg > + > + clocks: > + maxItems: 1 > + description: > + DP bridge clock, used by the IP to know how to translate a number of > + clock cycles into a time (which is used to comply with DP standard timings > + and delays). > + > + phys: > + maxItems: 1 > + description: > + phandle to the DisplayPort PHY. > + > + ports: > + type: object > + description: > + Ports as described in Documentation/devicetree/bindings/graph.txt. > + > + properties: > + '#address-cells': > + const: 1 > + > + '#size-cells': > + const: 0 > + > + port@0: > + type: object > + description: > + Input port representing the DP bridge input. > + > + port@1: > + type: object > + description: > + Output port representing the DP bridge output. I've got a chance to study the J721E datasheet, and it shows the DP bridge has 4 inputs, to support MST. Shouldn't this already be reflected in the DT bindings ? I think it should be as simple as having 4 input ports (port@0 to port@3) and one output port (port@4). The bindings are ABI, so care must be taken to support all features and avoid future changes that would break backward compatibility. It's fine if the driver doesn't implement this feature yet. > + > + required: > + - port@0 > + - port@1 > + - '#address-cells' > + - '#size-cells' > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: ti,j721e-mhdp8546 > + then: > + properties: > + reg: > + minItems: 2 > + reg-names: > + minItems: 2 > + else: > + properties: > + reg: > + maxItems: 1 > + reg-names: > + maxItems: 1 > + > +required: > + - compatible > + - clocks > + - reg > + - reg-names > + - phys > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + bus { > + #address-cells = <2>; > + #size-cells = <2>; > + > + mhdp: dp-bridge@f0fb000000 { > + compatible = "cdns,mhdp8546"; > + reg = <0xf0 0xfb000000 0x0 0x1000000>; > + reg-names = "mhdptx"; > + clocks = <&mhdp_clock>; > + phys = <&dp_phy>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dp_bridge_input: endpoint { > + remote-endpoint = <&xxx_dpi_output>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dp_bridge_output: endpoint { > + remote-endpoint = <&xxx_dp_connector_input>; > + }; > + }; > + }; > + }; > + }; > +...
On 11/08/2020 03:36, Laurent Pinchart wrote: > I've got a chance to study the J721E datasheet, and it shows the DP > bridge has 4 inputs, to support MST. Shouldn't this already be reflected > in the DT bindings ? I think it should be as simple as having 4 input > ports (port@0 to port@3) and one output port (port@4). I think this is a good point, mhdp has 4 input streams. Tomi
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml new file mode 100644 index 000000000000..dabccefe0983 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Cadence MHDP bridge + +maintainers: + - Swapnil Jakhade <sjakhade@cadence.com> + - Yuti Amonkar <yamonkar@cadence.com> + +properties: + compatible: + enum: + - cdns,mhdp8546 + - ti,j721e-mhdp8546 + + reg: + minItems: 1 + maxItems: 2 + items: + - description: + Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P). + The AUX and PMA registers are not part of this range, they are instead + included in the associated PHY. + - description: + Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs. + + reg-names: + minItems: 1 + maxItems: 2 + items: + - const: mhdptx + - const: j721e-intg + + clocks: + maxItems: 1 + description: + DP bridge clock, used by the IP to know how to translate a number of + clock cycles into a time (which is used to comply with DP standard timings + and delays). + + phys: + maxItems: 1 + description: + phandle to the DisplayPort PHY. + + ports: + type: object + description: + Ports as described in Documentation/devicetree/bindings/graph.txt. + + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + port@0: + type: object + description: + Input port representing the DP bridge input. + + port@1: + type: object + description: + Output port representing the DP bridge output. + + required: + - port@0 + - port@1 + - '#address-cells' + - '#size-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: ti,j721e-mhdp8546 + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + +required: + - compatible + - clocks + - reg + - reg-names + - phys + - ports + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + mhdp: dp-bridge@f0fb000000 { + compatible = "cdns,mhdp8546"; + reg = <0xf0 0xfb000000 0x0 0x1000000>; + reg-names = "mhdptx"; + clocks = <&mhdp_clock>; + phys = <&dp_phy>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp_bridge_input: endpoint { + remote-endpoint = <&xxx_dpi_output>; + }; + }; + + port@1 { + reg = <1>; + dp_bridge_output: endpoint { + remote-endpoint = <&xxx_dp_connector_input>; + }; + }; + }; + }; + }; +...