| Message ID | 20200814035819.1214-1-jiangyifei@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Fix bug in getting trap cause name for trace_riscv_trap | expand |
Patchew URL: https://patchew.org/QEMU/20200814035819.1214-1-jiangyifei@huawei.com/
Hi,
This series failed the docker-quick@centos7 build test. Please find the testing commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
=== TEST SCRIPT BEGIN ===
#!/bin/bash
make docker-image-centos7 V=1 NETWORK=1
time make docker-test-quick@centos7 SHOW_ENV=1 J=14 NETWORK=1
=== TEST SCRIPT END ===
TEST check-unit: tests/test-char
Unexpected error in object_property_try_add() at /tmp/qemu-test/src/qom/object.c:1181:
attempt to add duplicate property 'serial-id' to object (type 'container')
ERROR test-char - too few tests run (expected 38, got 9)
make: *** [check-unit] Error 1
make: *** Waiting for unfinished jobs....
TEST iotest-qcow2: 029
TEST check-qtest-x86_64: tests/qtest/hd-geo-test
---
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['sudo', '-n', 'docker', 'run', '--label', 'com.qemu.instance.uuid=83e8be982fe84f739b342435f33b62f6', '-u', '1003', '--security-opt', 'seccomp=unconfined', '--rm', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=14', '-e', 'DEBUG=', '-e', 'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/home/patchew2/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-brxkol53/src/docker-src.2020-08-14-00.10.36.6152:/var/tmp/qemu:z,ro', 'qemu/centos7', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit status 2.
filter=--filter=label=com.qemu.instance.uuid=83e8be982fe84f739b342435f33b62f6
make[1]: *** [docker-run] Error 1
make[1]: Leaving directory `/var/tmp/patchew-tester-tmp-brxkol53/src'
make: *** [docker-run-test-quick@centos7] Error 2
real 13m15.058s
user 0m8.409s
The full log is available at
http://patchew.org/logs/20200814035819.1214-1-jiangyifei@huawei.com/testing.docker-quick@centos7/?type=message.
---
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Please send your feedback to patchew-devel@redhat.com
On Thu, Aug 13, 2020 at 9:00 PM Yifei Jiang <jiangyifei@huawei.com> wrote: > > When the cause number is equal to or greater than 23, print "(unknown)" in > trace_riscv_trap. The max valid number of riscv_excp_names is 23, so the last > excpetion "guest_store_page_fault" can not be printed. > > In addition, the current check of cause is invalid for riscv_intr_names. So > introduce riscv_cpu_get_trap_name to get the trap cause name. > > Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> > Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 11 +++++++++++ > target/riscv/cpu.h | 1 + > target/riscv/cpu_helper.c | 4 ++-- > 3 files changed, 14 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 228b9bdb5d..bcdce85c5e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -96,6 +96,17 @@ const char * const riscv_intr_names[] = { > "reserved" > }; > > +const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) > +{ > + if (async) { > + return (cause < ARRAY_SIZE(riscv_intr_names)) ? > + riscv_intr_names[cause] : "(unknown)"; > + } else { > + return (cause < ARRAY_SIZE(riscv_excp_names)) ? > + riscv_excp_names[cause] : "(unknown)"; > + } > +} > + > static void set_misa(CPURISCVState *env, target_ulong misa) > { > env->misa_mask = env->misa = misa; > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index a804a5d0ba..7c72979f6a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -312,6 +312,7 @@ extern const char * const riscv_fpr_regnames[]; > extern const char * const riscv_excp_names[]; > extern const char * const riscv_intr_names[]; > > +const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); > void riscv_cpu_do_interrupt(CPUState *cpu); > int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 75d2ae3434..2e047f0948 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -877,8 +877,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) > } > } > > - trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ? > - (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); > + trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, > + riscv_cpu_get_trap_name(cause, async)); > > if (env->priv <= PRV_S && > cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) { > -- > 2.19.1 > > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 228b9bdb5d..bcdce85c5e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -96,6 +96,17 @@ const char * const riscv_intr_names[] = { "reserved" }; +const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) +{ + if (async) { + return (cause < ARRAY_SIZE(riscv_intr_names)) ? + riscv_intr_names[cause] : "(unknown)"; + } else { + return (cause < ARRAY_SIZE(riscv_excp_names)) ? + riscv_excp_names[cause] : "(unknown)"; + } +} + static void set_misa(CPURISCVState *env, target_ulong misa) { env->misa_mask = env->misa = misa; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a804a5d0ba..7c72979f6a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -312,6 +312,7 @@ extern const char * const riscv_fpr_regnames[]; extern const char * const riscv_excp_names[]; extern const char * const riscv_intr_names[]; +const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 75d2ae3434..2e047f0948 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -877,8 +877,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) } } - trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, cause < 23 ? - (async ? riscv_intr_names : riscv_excp_names)[cause] : "(unknown)"); + trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, + riscv_cpu_get_trap_name(cause, async)); if (env->priv <= PRV_S && cause < TARGET_LONG_BITS && ((deleg >> cause) & 1)) {