Message ID | 942144b9b030b0cafd07bb019347f26403734600.1597768760.git.chunkeey@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v1,1/6] dt-bindings: ARM: add bindings for the Meraki MR32 | expand |
On 2020-08-18 9:39 a.m., Christian Lamparter wrote: > The SoC supports three pcie ports. Currently, only > pcie0 and pcie1 are enabled. This patch adds the > pcie2 port as well. > > Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com> > --- > arch/arm/boot/dts/bcm5301x.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi > index 45f5b35fa02b..f7bd1587e285 100644 > --- a/arch/arm/boot/dts/bcm5301x.dtsi > +++ b/arch/arm/boot/dts/bcm5301x.dtsi > @@ -252,6 +252,10 @@ pcie1: pcie@13000 { > reg = <0x00013000 0x1000>; > }; > > + pcie2: pcie@14000 { > + reg = <0x00014000 0x1000>; > + }; > + > usb2: usb2@21000 { > reg = <0x00021000 0x1000>; >
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 45f5b35fa02b..f7bd1587e285 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -252,6 +252,10 @@ pcie1: pcie@13000 { reg = <0x00013000 0x1000>; }; + pcie2: pcie@14000 { + reg = <0x00014000 0x1000>; + }; + usb2: usb2@21000 { reg = <0x00021000 0x1000>;
The SoC supports three pcie ports. Currently, only pcie0 and pcie1 are enabled. This patch adds the pcie2 port as well. Signed-off-by: Christian Lamparter <chunkeey@gmail.com> --- arch/arm/boot/dts/bcm5301x.dtsi | 4 ++++ 1 file changed, 4 insertions(+)