| Message ID | 20200723084628.19241-2-lokeshvutla@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: Initial support for Texas Instrument's J7200 Platform | expand |
On 14:16-20200723, Lokesh Vutla wrote: > The J7200 SoC is a part of the K3 Multicore SoC architecture platform. > It is targeted for automotive gateway, vehicle compute systems, > Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. > The SoC aims to meet the complex processing needs of modern embedded > products. > > Some highlights of this SoC are: > * Dual Cortex-A72s in a single cluster, two clusters of lockstep > capable dual Cortex-R5F MCUs and a Centralized Device Management and > Security Controller (DMSC). > * Configurable L3 Cache and IO-coherent architecture with high data > throughput capable distributed DMA architecture under NAVSS. > * Integrated Ethernet switch supporting up to a total of 4 external ports > in addition to legacy Ethernet switch of up to 2 ports. > * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, > 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and > I2C, eCAP/eQEP, eHRPWM among other peripherals. > * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL > management. > > See J7200 Technical Reference Manual (SPRUIU1, June 2020) > for further details: https://www.ti.com/lit/pdf/spruiu1 > > Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> > --- > Documentation/devicetree/bindings/arm/ti/k3.txt | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt > index 333e7256126a..33419cce0afa 100644 > --- a/Documentation/devicetree/bindings/arm/ti/k3.txt > +++ b/Documentation/devicetree/bindings/arm/ti/k3.txt > @@ -16,6 +16,9 @@ architecture it uses, using one of the following compatible values: > - J721E > compatible = "ti,j721e"; > > +- J7200 > + compatible = "ti,j7200"; > + > Boards > ------ Lets convert the k3.txt to k3.yaml before we do anything more here. Looking at the full series, I see that there are pending comments from Grygorii as well which needs to be looked at. I have'nt seen a follow up version since this version. [1] https://lore.kernel.org/linux-arm-kernel/20200723084628.19241-1-lokeshvutla@ti.com/
Hi Nishanth, On 27/08/20 5:53 am, Nishanth Menon wrote: > On 14:16-20200723, Lokesh Vutla wrote: >> The J7200 SoC is a part of the K3 Multicore SoC architecture platform. >> It is targeted for automotive gateway, vehicle compute systems, >> Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. >> The SoC aims to meet the complex processing needs of modern embedded >> products. >> >> Some highlights of this SoC are: >> * Dual Cortex-A72s in a single cluster, two clusters of lockstep >> capable dual Cortex-R5F MCUs and a Centralized Device Management and >> Security Controller (DMSC). >> * Configurable L3 Cache and IO-coherent architecture with high data >> throughput capable distributed DMA architecture under NAVSS. >> * Integrated Ethernet switch supporting up to a total of 4 external ports >> in addition to legacy Ethernet switch of up to 2 ports. >> * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, >> 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and >> I2C, eCAP/eQEP, eHRPWM among other peripherals. >> * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL >> management. >> >> See J7200 Technical Reference Manual (SPRUIU1, June 2020) >> for further details: https://www.ti.com/lit/pdf/spruiu1 >> >> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> >> --- >> Documentation/devicetree/bindings/arm/ti/k3.txt | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt >> index 333e7256126a..33419cce0afa 100644 >> --- a/Documentation/devicetree/bindings/arm/ti/k3.txt >> +++ b/Documentation/devicetree/bindings/arm/ti/k3.txt >> @@ -16,6 +16,9 @@ architecture it uses, using one of the following compatible values: >> - J721E >> compatible = "ti,j721e"; >> >> +- J7200 >> + compatible = "ti,j7200"; >> + >> Boards >> ------ > > Lets convert the k3.txt to k3.yaml before we do anything more here. > Looking at the full series, I see that there are pending comments from okay, I can switch Patch 1 and 2. > Grygorii as well which needs to be looked at. I have'nt seen a follow up > version since this version. Grygorii replied to the same asking to ignore his mail[0] [0] https://patchwork.kernel.org/cover/11680441/ Thanks and regards, Lokesh > > [1] https://lore.kernel.org/linux-arm-kernel/20200723084628.19241-1-lokeshvutla@ti.com/ >
diff --git a/Documentation/devicetree/bindings/arm/ti/k3.txt b/Documentation/devicetree/bindings/arm/ti/k3.txt index 333e7256126a..33419cce0afa 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.txt +++ b/Documentation/devicetree/bindings/arm/ti/k3.txt @@ -16,6 +16,9 @@ architecture it uses, using one of the following compatible values: - J721E compatible = "ti,j721e"; +- J7200 + compatible = "ti,j7200"; + Boards ------
The J7200 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, two clusters of lockstep capable dual Cortex-R5F MCUs and a Centralized Device Management and Security Controller (DMSC). * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS. * Integrated Ethernet switch supporting up to a total of 4 external ports in addition to legacy Ethernet switch of up to 2 ports. * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and I2C, eCAP/eQEP, eHRPWM among other peripherals. * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> --- Documentation/devicetree/bindings/arm/ti/k3.txt | 3 +++ 1 file changed, 3 insertions(+)