| Message ID | 20200825160603.32388-3-wei.chen@arm.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Fix Guest random crash on Cortex-N1/A76/A75 cores | expand |
> On 25 Aug 2020, at 17:06, Wei Chen <Wei.Chen@arm.com> wrote: > > Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU > FP/SIMD implementations. Currently, we exactly know the meaning of > 0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD > features presented. If there is a value 0x2 bumped in the future, > Xen behaviors for value <= 0x1 can also take effect. But what Xen > done for value <= 0x1 may not always cover new value 0x2 required. > We throw these messages to break the silence when Xen detected > unknown FP/SIMD IDs to notice user to check. > > Signed-off-by: Wei Chen <wei.chen@arm.com> With the small typo after fixed: Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com> > --- > xen/arch/arm/setup.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c > index 7968cee47d..6a31eca984 100644 > --- a/xen/arch/arm/setup.c > +++ b/xen/arch/arm/setup.c > @@ -133,6 +133,18 @@ static void __init processor_id(void) > cpu_has_simd ? " AdvancedSIMD" : "", > cpu_has_gicv3 ? " GICv3-SysReg" : ""); > > + /* Warn user if we find unknown floating-point features */ > + if ( cpu_has_fp && (boot_cpu_feature64(fp) >= 2) ) > + printk(XENLOG_WARNING "WARNING: Unknown Floating-point ID:%d, " > + "this may result to corruption on the platform\n", s/to/in/ > + boot_cpu_feature64(fp)); > + > + /* Warn user if we find unknown AdvancedSIMD features */ > + if ( cpu_has_simd && (boot_cpu_feature64(simd) >= 2) ) > + printk(XENLOG_WARNING "WARNING: Unknown AdvancedSIMD ID:%d, " > + "this may result to corruption on the platform\n", same as upper > + boot_cpu_feature64(simd)); > + > printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n", > boot_cpu_data.dbg64.bits[0], boot_cpu_data.dbg64.bits[1]); > printk(" Auxiliary Features: %016"PRIx64" %016"PRIx64"\n", > -- > 2.17.1 >
Hi, On 25/08/2020 17:06, Wei Chen wrote: > Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU > FP/SIMD implementations. Currently, we exactly know the meaning of > 0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD > features presented. If there is a value 0x2 bumped in the future, > Xen behaviors for value <= 0x1 can also take effect. But what Xen > done for value <= 0x1 may not always cover new value 0x2 required. > We throw these messages to break the silence when Xen detected > unknown FP/SIMD IDs to notice user to check. > > Signed-off-by: Wei Chen <wei.chen@arm.com> Acked-by: Julien Grall <jgrall@amazon.com> Cheers,
Hi Bertand, > -----Original Message----- > From: Bertrand Marquis <Bertrand.Marquis@arm.com> > Sent: 2020年8月27日 22:13 > To: Wei Chen <Wei.Chen@arm.com> > Cc: Xen-devel <xen-devel@lists.xenproject.org>; sstabellini@kernel.org; > julien@xen.org; Andre Przywara <Andre.Przywara@arm.com>; Penny Zheng > <Penny.Zheng@arm.com>; Kaly Xin <Kaly.Xin@arm.com>; nd <nd@arm.com> > Subject: Re: [PATCH v4 2/2] xen/arm: Throw messages for unknown > FP/SIMD implement ID > > > > > On 25 Aug 2020, at 17:06, Wei Chen <Wei.Chen@arm.com> wrote: > > > > Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU > > FP/SIMD implementations. Currently, we exactly know the meaning of > > 0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD > > features presented. If there is a value 0x2 bumped in the future, > > Xen behaviors for value <= 0x1 can also take effect. But what Xen > > done for value <= 0x1 may not always cover new value 0x2 required. > > We throw these messages to break the silence when Xen detected > > unknown FP/SIMD IDs to notice user to check. > > > > Signed-off-by: Wei Chen <wei.chen@arm.com> > > With the small typo after fixed: > Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com> > > > --- > > xen/arch/arm/setup.c | 12 ++++++++++++ > > 1 file changed, 12 insertions(+) > > > > diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c > > index 7968cee47d..6a31eca984 100644 > > --- a/xen/arch/arm/setup.c > > +++ b/xen/arch/arm/setup.c > > @@ -133,6 +133,18 @@ static void __init processor_id(void) > > cpu_has_simd ? " AdvancedSIMD" : "", > > cpu_has_gicv3 ? " GICv3-SysReg" : ""); > > > > + /* Warn user if we find unknown floating-point features */ > > + if ( cpu_has_fp && (boot_cpu_feature64(fp) >= 2) ) > > + printk(XENLOG_WARNING "WARNING: Unknown Floating-point > ID:%d, " > > + "this may result to corruption on the platform\n", > > s/to/in/ > > > + boot_cpu_feature64(fp)); > > + > > + /* Warn user if we find unknown AdvancedSIMD features */ > > + if ( cpu_has_simd && (boot_cpu_feature64(simd) >= 2) ) > > + printk(XENLOG_WARNING "WARNING: Unknown AdvancedSIMD > ID:%d, " > > + "this may result to corruption on the platform\n", > > same as upper I would fix above two typos and send a new version. > > > + boot_cpu_feature64(simd)); > > + > > printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n", > > boot_cpu_data.dbg64.bits[0], boot_cpu_data.dbg64.bits[1]); > > printk(" Auxiliary Features: %016"PRIx64" %016"PRIx64"\n", > > -- > > 2.17.1 > > > >
diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 7968cee47d..6a31eca984 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -133,6 +133,18 @@ static void __init processor_id(void) cpu_has_simd ? " AdvancedSIMD" : "", cpu_has_gicv3 ? " GICv3-SysReg" : ""); + /* Warn user if we find unknown floating-point features */ + if ( cpu_has_fp && (boot_cpu_feature64(fp) >= 2) ) + printk(XENLOG_WARNING "WARNING: Unknown Floating-point ID:%d, " + "this may result to corruption on the platform\n", + boot_cpu_feature64(fp)); + + /* Warn user if we find unknown AdvancedSIMD features */ + if ( cpu_has_simd && (boot_cpu_feature64(simd) >= 2) ) + printk(XENLOG_WARNING "WARNING: Unknown AdvancedSIMD ID:%d, " + "this may result to corruption on the platform\n", + boot_cpu_feature64(simd)); + printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n", boot_cpu_data.dbg64.bits[0], boot_cpu_data.dbg64.bits[1]); printk(" Auxiliary Features: %016"PRIx64" %016"PRIx64"\n",
Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU FP/SIMD implementations. Currently, we exactly know the meaning of 0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD features presented. If there is a value 0x2 bumped in the future, Xen behaviors for value <= 0x1 can also take effect. But what Xen done for value <= 0x1 may not always cover new value 0x2 required. We throw these messages to break the silence when Xen detected unknown FP/SIMD IDs to notice user to check. Signed-off-by: Wei Chen <wei.chen@arm.com> --- xen/arch/arm/setup.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)