diff mbox series

[v6,2/7] drm/i915: Add support for async flips in I915

Message ID 20200807093551.10673-3-karthik.b.s@intel.com (mailing list archive)
State New, archived
Headers show
Series Asynchronous flip implementation for i915 | expand

Commit Message

Karthik B S Aug. 7, 2020, 9:35 a.m. UTC
Set the Async Address Update Enable bit in plane ctl
when async flip is requested.

v2: -Move the Async flip enablement to individual patch (Paulo)

v3: -Rebased.

v4: -Add separate plane hook for async flip case (Ville)

v5: -Rebased.

v6: -Move the plane hook to separate patch. (Paulo)
    -Remove the early return in skl_plane_ctl. (Paulo)

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h              | 1 +
 2 files changed, 4 insertions(+)

Comments

Ville Syrjälä Sept. 1, 2020, 11:15 a.m. UTC | #1
On Fri, Aug 07, 2020 at 03:05:46PM +0530, Karthik B S wrote:
> Set the Async Address Update Enable bit in plane ctl
> when async flip is requested.
> 
> v2: -Move the Async flip enablement to individual patch (Paulo)
> 
> v3: -Rebased.
> 
> v4: -Add separate plane hook for async flip case (Ville)
> 
> v5: -Rebased.
> 
> v6: -Move the plane hook to separate patch. (Paulo)
>     -Remove the early return in skl_plane_ctl. (Paulo)
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h              | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1ac2e6f27597..ce2b0c14a073 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4768,6 +4768,9 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  
>  	plane_ctl = PLANE_CTL_ENABLE;
>  
> +	if (crtc_state->uapi.async_flip)
> +		plane_ctl |= PLANE_CTL_ASYNC_FLIP;

Hmm. We might want to put that into skl_plane_ctl_crtc() since it's
a crtc-wide thing,

> +
>  	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
>  		plane_ctl |= skl_plane_ctl_alpha(plane_state);
>  		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e85c6fc1f3cb..3f88d9ac90a8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6924,6 +6924,7 @@ enum {
>  #define   PLANE_CTL_TILED_X			(1 << 10)
>  #define   PLANE_CTL_TILED_Y			(4 << 10)
>  #define   PLANE_CTL_TILED_YF			(5 << 10)
> +#define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
>  #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
>  #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
>  #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
> -- 
> 2.22.0
Karthik B S Sept. 2, 2020, 1:28 p.m. UTC | #2
On 9/1/2020 4:45 PM, Ville Syrjälä wrote:
> On Fri, Aug 07, 2020 at 03:05:46PM +0530, Karthik B S wrote:
>> Set the Async Address Update Enable bit in plane ctl
>> when async flip is requested.
>>
>> v2: -Move the Async flip enablement to individual patch (Paulo)
>>
>> v3: -Rebased.
>>
>> v4: -Add separate plane hook for async flip case (Ville)
>>
>> v5: -Rebased.
>>
>> v6: -Move the plane hook to separate patch. (Paulo)
>>      -Remove the early return in skl_plane_ctl. (Paulo)
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>>   drivers/gpu/drm/i915/i915_reg.h              | 1 +
>>   2 files changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 1ac2e6f27597..ce2b0c14a073 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -4768,6 +4768,9 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>>   
>>   	plane_ctl = PLANE_CTL_ENABLE;
>>   
>> +	if (crtc_state->uapi.async_flip)
>> +		plane_ctl |= PLANE_CTL_ASYNC_FLIP;
> 
> Hmm. We might want to put that into skl_plane_ctl_crtc() since it's
> a crtc-wide thing,
> 

Thanks for the review.
Sure, I'll move this.

Thanks,
Karthik.B.S
>> +
>>   	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
>>   		plane_ctl |= skl_plane_ctl_alpha(plane_state);
>>   		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index e85c6fc1f3cb..3f88d9ac90a8 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6924,6 +6924,7 @@ enum {
>>   #define   PLANE_CTL_TILED_X			(1 << 10)
>>   #define   PLANE_CTL_TILED_Y			(4 << 10)
>>   #define   PLANE_CTL_TILED_YF			(5 << 10)
>> +#define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
>>   #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
>>   #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
>>   #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
>> -- 
>> 2.22.0
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1ac2e6f27597..ce2b0c14a073 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4768,6 +4768,9 @@  u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 
 	plane_ctl = PLANE_CTL_ENABLE;
 
+	if (crtc_state->uapi.async_flip)
+		plane_ctl |= PLANE_CTL_ASYNC_FLIP;
+
 	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
 		plane_ctl |= skl_plane_ctl_alpha(plane_state);
 		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e85c6fc1f3cb..3f88d9ac90a8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6924,6 +6924,7 @@  enum {
 #define   PLANE_CTL_TILED_X			(1 << 10)
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
+#define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
 #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */