[V2,14/46] x86/ioapic: Consolidate IOAPIC allocation

Message ID	20200826112332.054367732@linutronix.de (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=oDxe=CE=lists.xenproject.org=xen-devel-bounces@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 32CEF20786 Message-Id: <20200826112332.054367732@linutronix.de> Date: Wed, 26 Aug 2020 13:16:42 +0200 From: Thomas Gleixner <tglx@linutronix.de> To: LKML <linux-kernel@vger.kernel.org> Cc: x86@kernel.org, Joerg Roedel <joro@8bytes.org>, iommu@lists.linux-foundation.org, linux-hyperv@vger.kernel.org, Haiyang Zhang <haiyangz@microsoft.com>, Jon Derrick <jonathan.derrick@intel.com>, Lu Baolu <baolu.lu@linux.intel.com>, Wei Liu <wei.liu@kernel.org>, "K. Y. Srinivasan" <kys@microsoft.com>, Stephen Hemminger <sthemmin@microsoft.com>, Steve Wahl <steve.wahl@hpe.com>, Dimitri Sivanich <sivanich@hpe.com>, Russ Anderson <rja@hpe.com>, linux-pci@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>, xen-devel@lists.xenproject.org, Juergen Gross <jgross@suse.com>, Boris Ostrovsky <boris.ostrovsky@oracle.com>, Stefano Stabellini <sstabellini@kernel.org>, Marc Zyngier <maz@kernel.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, "Rafael J. Wysocki" <rafael@kernel.org>, Megha Dey <megha.dey@intel.com>, Jason Gunthorpe <jgg@mellanox.com>, Dave Jiang <dave.jiang@intel.com>, Alex Williamson <alex.williamson@redhat.com>, Jacob Pan <jacob.jun.pan@intel.com>, Baolu Lu <baolu.lu@intel.com>, Kevin Tian <kevin.tian@intel.com>, Dan Williams <dan.j.williams@intel.com> Subject: [patch V2 14/46] x86/ioapic: Consolidate IOAPIC allocation References: <20200826111628.794979401@linutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-transfer-encoding: 8-bit Precedence: list Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" <xen-devel-bounces@lists.xenproject.org>
Series	x86, PCI, XEN, genirq ...: Prepare for device MSI \| expand [V2,00/46] x86, PCI, XEN, genirq ...: Prepare for device MSI [V2,01/46] iommu/amd: Prevent NULL pointer dereference [V2,02/46] x86/init: Remove unused init ops [V2,03/46] PCI: vmd: Dont abuse vector irqomain as parent [V2,04/46] genirq/chip: Use the first chip in irq_chip_compose_msi_msg() [V2,05/46] x86/msi: Move compose message callback where it belongs [V2,06/46] x86/msi: Remove pointless vcpu_affinity callback [V2,07/46] x86/irq: Rename X86_IRQ_ALLOC_TYPE_MSI* to reflect PCI dependency [V2,08/46] x86/irq: Add allocation type for parent domain retrieval [V2,09/46] iommu/vt-d: Consolidate irq domain getter [V2,10/46] iommu/amd: Consolidate irq domain getter [V2,11/46] iommu/irq_remapping: Consolidate irq domain lookup [V2,12/46] x86/irq: Prepare consolidation of irq_alloc_info [V2,13/46] x86/msi: Consolidate HPET allocation [V2,14/46] x86/ioapic: Consolidate IOAPIC allocation [V2,15/46] x86/irq: Consolidate DMAR irq allocation [V2,16/46] x86/irq: Consolidate UV domain allocation [V2,17/46] PCI/MSI: Rework pci_msi_domain_calc_hwirq() [V2,18/46] x86/msi: Consolidate MSI allocation [V2,19/46] x86/msi: Use generic MSI domain ops [V2,20/46] x86/irq: Move apic_post_init() invocation to one place [V2,21/46] x86/pci: Reducde #ifdeffery in PCI init code [V2,22/46] x86/irq: Initialize PCI/MSI domain at PCI init time [V2,23/46] irqdomain/msi: Provide DOMAIN_BUS_VMD_MSI [V2,24/46] PCI: vmd: Mark VMD irqdomain with DOMAIN_BUS_VMD_MSI [V2,25/46] PCI/MSI: Provide pci_dev_has_special_msi_domain() helper [V2,26/46] x86/xen: Make xen_msi_init() static and rename it to xen_hvm_msi_init() [V2,27/46] x86/xen: Rework MSI teardown [V2,28/46] x86/xen: Consolidate XEN-MSI init [V2,29/46] irqdomain/msi: Allow to override msi_domain_alloc/free_irqs() [V2,30/46] x86/xen: Wrap XEN MSI management into irqdomain [V2,31/46] iommm/vt-d: Store irq domain in struct device [V2,32/46] iommm/amd: Store irq domain in struct device [V2,33/46] x86/pci: Set default irq domain in pcibios_add_device() [V2,34/46] PCI/MSI: Make arch_._msi_irq[s] fallbacks selectable [V2,35/46] x86/irq: Cleanup the arch__msi_irqs() leftovers [V2,36/46] x86/irq: Make most MSI ops XEN private [V2,37/46] iommu/vt-d: Remove domain search for PCI/MSI[X] [V2,38/46] iommu/amd: Remove domain search for PCI/MSI [V2,39/46] x86/irq: Add DEV_MSI allocation type [V2,40/46] x86/msi: Rename and rework pci_msi_prepare() to cover non-PCI MSI [V2,41/46] platform-msi: Provide default irq_chip:: Ack [V2,42/46] genirq/proc: Take buslock on affinity write [V2,43/46] genirq/msi: Provide and use msi_domain_set_default_info_flags() [V2,44/46] platform-msi: Add device MSI infrastructure [V2,45/46] irqdomain/msi: Provide msi_alloc/free_store() callbacks [V2,46/46] irqchip: Add IMS (Interrupt Message Storm) driver - NOT FOR MERGING

--- a/arch/x86/include/asm/hw_irq.h +++ b/arch/x86/include/asm/hw_irq.h @@ -44,6 +44,15 @@ enum irq_alloc_type { X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT, }; +struct ioapic_alloc_info { + int pin; + int node; + u32 trigger : 1; + u32 polarity : 1; + u32 valid : 1; + struct IO_APIC_route_entry *entry; +}; + /** * irq_alloc_info - X86 specific interrupt allocation info * @type: X86 specific allocation type @@ -53,6 +62,8 @@ enum irq_alloc_type { * @mask: CPU mask for vector allocation * @desc: Pointer to msi descriptor * @data: Allocation specific data + * + * @ioapic: IOAPIC specific allocation data */ struct irq_alloc_info { enum irq_alloc_type type; @@ -64,6 +75,7 @@ struct irq_alloc_info { void *data; union { + struct ioapic_alloc_info ioapic; int unused; #ifdef CONFIG_PCI_MSI struct { @@ -71,17 +83,6 @@ struct irq_alloc_info { irq_hw_number_t msi_hwirq; }; #endif -#ifdef CONFIG_X86_IO_APIC - struct { - int ioapic_id; - int ioapic_pin; - int ioapic_node; - u32 ioapic_trigger : 1; - u32 ioapic_polarity : 1; - u32 ioapic_valid : 1; - struct IO_APIC_route_entry *ioapic_entry; - }; -#endif #ifdef CONFIG_DMAR_TABLE struct { int dmar_id; --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -860,10 +860,10 @@ void ioapic_set_alloc_attr(struct irq_al { init_irq_alloc_info(info, NULL); info->type = X86_IRQ_ALLOC_TYPE_IOAPIC; - info->ioapic_node = node; - info->ioapic_trigger = trigger; - info->ioapic_polarity = polarity; - info->ioapic_valid = 1; + info->ioapic.node = node; + info->ioapic.trigger = trigger; + info->ioapic.polarity = polarity; + info->ioapic.valid = 1; } #ifndef CONFIG_ACPI @@ -878,32 +878,32 @@ static void ioapic_copy_alloc_attr(struc copy_irq_alloc_info(dst, src); dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC; - dst->ioapic_id = mpc_ioapic_id(ioapic_idx); - dst->ioapic_pin = pin; - dst->ioapic_valid = 1; - if (src && src->ioapic_valid) { - dst->ioapic_node = src->ioapic_node; - dst->ioapic_trigger = src->ioapic_trigger; - dst->ioapic_polarity = src->ioapic_polarity; + dst->devid = mpc_ioapic_id(ioapic_idx); + dst->ioapic.pin = pin; + dst->ioapic.valid = 1; + if (src && src->ioapic.valid) { + dst->ioapic.node = src->ioapic.node; + dst->ioapic.trigger = src->ioapic.trigger; + dst->ioapic.polarity = src->ioapic.polarity; } else { - dst->ioapic_node = NUMA_NO_NODE; + dst->ioapic.node = NUMA_NO_NODE; if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) { - dst->ioapic_trigger = trigger; - dst->ioapic_polarity = polarity; + dst->ioapic.trigger = trigger; + dst->ioapic.polarity = polarity; } else { /* * PCI interrupts are always active low level * triggered. */ - dst->ioapic_trigger = IOAPIC_LEVEL; - dst->ioapic_polarity = IOAPIC_POL_LOW; + dst->ioapic.trigger = IOAPIC_LEVEL; + dst->ioapic.polarity = IOAPIC_POL_LOW; } } } static int ioapic_alloc_attr_node(struct irq_alloc_info *info) { - return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE; + return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE; } static void mp_register_handler(unsigned int irq, unsigned long trigger) @@ -933,14 +933,14 @@ static bool mp_check_pin_attr(int irq, s * pin with real trigger and polarity attributes. */ if (irq < nr_legacy_irqs() && data->count == 1) { - if (info->ioapic_trigger != data->trigger) - mp_register_handler(irq, info->ioapic_trigger); - data->entry.trigger = data->trigger = info->ioapic_trigger; - data->entry.polarity = data->polarity = info->ioapic_polarity; + if (info->ioapic.trigger != data->trigger) + mp_register_handler(irq, info->ioapic.trigger); + data->entry.trigger = data->trigger = info->ioapic.trigger; + data->entry.polarity = data->polarity = info->ioapic.polarity; } - return data->trigger == info->ioapic_trigger && - data->polarity == info->ioapic_polarity; + return data->trigger == info->ioapic.trigger && + data->polarity == info->ioapic.polarity; } static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi, @@ -1002,7 +1002,7 @@ static int alloc_isa_irq_from_domain(str if (!mp_check_pin_attr(irq, info)) return -EBUSY; if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic, - info->ioapic_pin)) + info->ioapic.pin)) return -ENOMEM; } else { info->flags |= X86_IRQ_ALLOC_LEGACY; @@ -2092,8 +2092,8 @@ static int mp_alloc_timer_irq(int ioapic struct irq_alloc_info info; ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0); - info.ioapic_id = mpc_ioapic_id(ioapic); - info.ioapic_pin = pin; + info.devid = mpc_ioapic_id(ioapic); + info.ioapic.pin = pin; mutex_lock(&ioapic_mutex); irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info); mutex_unlock(&ioapic_mutex); @@ -2297,7 +2297,7 @@ static int mp_irqdomain_create(int ioapi init_irq_alloc_info(&info, NULL); info.type = X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT; - info.ioapic_id = mpc_ioapic_id(ioapic); + info.devid = mpc_ioapic_id(ioapic); parent = irq_remapping_get_irq_domain(&info); if (!parent) parent = x86_vector_domain; @@ -2932,9 +2932,9 @@ int mp_ioapic_registered(u32 gsi_base) static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data, struct irq_alloc_info *info) { - if (info && info->ioapic_valid) { - data->trigger = info->ioapic_trigger; - data->polarity = info->ioapic_polarity; + if (info && info->ioapic.valid) { + data->trigger = info->ioapic.trigger; + data->polarity = info->ioapic.polarity; } else if (acpi_get_override_irq(gsi, &data->trigger, &data->polarity) < 0) { /* PCI interrupts are always active low level triggered. */ @@ -2980,7 +2980,7 @@ int mp_irqdomain_alloc(struct irq_domain return -EINVAL; ioapic = mp_irqdomain_ioapic_idx(domain); - pin = info->ioapic_pin; + pin = info->ioapic.pin; if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0) return -EEXIST; @@ -2988,7 +2988,7 @@ int mp_irqdomain_alloc(struct irq_domain if (!data) return -ENOMEM; - info->ioapic_entry = &data->entry; + info->ioapic.entry = &data->entry; ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info); if (ret < 0) { kfree(data); @@ -2996,7 +2996,7 @@ int mp_irqdomain_alloc(struct irq_domain } INIT_LIST_HEAD(&data->irq_2_pin); - irq_data->hwirq = info->ioapic_pin; + irq_data->hwirq = info->ioapic.pin; irq_data->chip = (domain->parent == x86_vector_domain) ? &ioapic_chip : &ioapic_ir_chip; irq_data->chip_data = data; @@ -3006,8 +3006,8 @@ int mp_irqdomain_alloc(struct irq_domain add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin); local_irq_save(flags); - if (info->ioapic_entry) - mp_setup_entry(cfg, data, info->ioapic_entry); + if (info->ioapic.entry) + mp_setup_entry(cfg, data, info->ioapic.entry); mp_register_handler(virq, data->trigger); if (virq < nr_legacy_irqs()) legacy_pic->mask(virq); --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -229,8 +229,8 @@ static int dt_irqdomain_alloc(struct irq it = &of_ioapic_type[type_index]; ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity); - tmp.ioapic_id = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain)); - tmp.ioapic_pin = fwspec->param[0]; + tmp.devid = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain)); + tmp.ioapic.pin = fwspec->param[0]; return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp); } --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3508,7 +3508,7 @@ static int get_devid(struct irq_alloc_in switch (info->type) { case X86_IRQ_ALLOC_TYPE_IOAPIC: case X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT: - return get_ioapic_devid(info->ioapic_id); + return get_ioapic_devid(info->devid); case X86_IRQ_ALLOC_TYPE_HPET: case X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT: return get_hpet_devid(info->devid); @@ -3586,15 +3586,15 @@ static void irq_remapping_prepare_irte(s switch (info->type) { case X86_IRQ_ALLOC_TYPE_IOAPIC: /* Setup IOAPIC entry */ - entry = info->ioapic_entry; - info->ioapic_entry = NULL; + entry = info->ioapic.entry; + info->ioapic.entry = NULL; memset(entry, 0, sizeof(*entry)); entry->vector = index; entry->mask = 0; - entry->trigger = info->ioapic_trigger; - entry->polarity = info->ioapic_polarity; + entry->trigger = info->ioapic.trigger; + entry->polarity = info->ioapic.polarity; /* Mask level triggered irqs. */ - if (info->ioapic_trigger) + if (info->ioapic.trigger) entry->mask = 1; break; @@ -3680,7 +3680,7 @@ static int irq_remapping_alloc(struct ir iommu->irte_ops->set_allocated(table, i); } WARN_ON(table->min_index != 32); - index = info->ioapic_pin; + index = info->ioapic.pin; } else { index = -ENOMEM; } --- a/drivers/iommu/hyperv-iommu.c +++ b/drivers/iommu/hyperv-iommu.c @@ -101,7 +101,7 @@ static int hyperv_irq_remapping_alloc(st * in the chip_data and hyperv_irq_remapping_activate()/hyperv_ir_set_ * affinity() set vector and dest_apicid directly into IO-APIC entry. */ - irq_data->chip_data = info->ioapic_entry; + irq_data->chip_data = info->ioapic.entry; /* * Hypver-V IO APIC irq affinity should be in the scope of --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1113,7 +1113,7 @@ static struct irq_domain *intel_get_irq_ switch (info->type) { case X86_IRQ_ALLOC_TYPE_IOAPIC_GET_PARENT: - return map_ioapic_to_ir(info->ioapic_id); + return map_ioapic_to_ir(info->devid); case X86_IRQ_ALLOC_TYPE_HPET_GET_PARENT: return map_hpet_to_ir(info->devid); case X86_IRQ_ALLOC_TYPE_PCI_MSI: @@ -1254,16 +1254,16 @@ static void intel_irq_remapping_prepare_ switch (info->type) { case X86_IRQ_ALLOC_TYPE_IOAPIC: /* Set source-id of interrupt request */ - set_ioapic_sid(irte, info->ioapic_id); + set_ioapic_sid(irte, info->devid); apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n", - info->ioapic_id, irte->present, irte->fpd, + info->devid, irte->present, irte->fpd, irte->dst_mode, irte->redir_hint, irte->trigger_mode, irte->dlvry_mode, irte->avail, irte->vector, irte->dest_id, irte->sid, irte->sq, irte->svt); - entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry; - info->ioapic_entry = NULL; + entry = (struct IR_IO_APIC_route_entry *)info->ioapic.entry; + info->ioapic.entry = NULL; memset(entry, 0, sizeof(*entry)); entry->index2 = (index >> 15) & 0x1; entry->zero = 0; @@ -1273,11 +1273,11 @@ static void intel_irq_remapping_prepare_ * IO-APIC RTE will be configured with virtual vector. * irq handler will do the explicit EOI to the io-apic. */ - entry->vector = info->ioapic_pin; + entry->vector = info->ioapic.pin; entry->mask = 0; /* enable IRQ */ - entry->trigger = info->ioapic_trigger; - entry->polarity = info->ioapic_polarity; - if (info->ioapic_trigger) + entry->trigger = info->ioapic.trigger; + entry->polarity = info->ioapic.polarity; + if (info->ioapic.trigger) entry->mask = 1; /* Mask level triggered irqs. */ break;

[V2,14/46] x86/ioapic: Consolidate IOAPIC allocation

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