diff mbox series

[v3,10/21] dt-bindings: arm: hisilicon: convert hisilicon, pcie-sas-subctrl bindings to json-schema

Message ID 20200927062129.4573-11-thunder.leizhen@huawei.com (mailing list archive)
State New, archived
Headers show
Series add support for Hisilicon SD5203 SoC | expand

Commit Message

Leizhen (ThunderTown) Sept. 27, 2020, 6:21 a.m. UTC 
Convert the Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller binding
to DT schema format using json-schema.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
---
 .../controller/hisilicon,pcie-sas-subctrl.txt      | 15 ---------
 .../controller/hisilicon,pcie-sas-subctrl.yaml     | 37 ++++++++++++++++++++++
 2 files changed, 37 insertions(+), 15 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
 create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml

Comments

Jonathan Cameron Sept. 28, 2020, 9:46 a.m. UTC | #1 
On Sun, 27 Sep 2020 14:21:18 +0800
Zhen Lei <thunder.leizhen@huawei.com> wrote:

> Convert the Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller binding
> to DT schema format using json-schema.
> 
> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>

One small thing inline to fix.

Jonathan

> ---
>  .../controller/hisilicon,pcie-sas-subctrl.txt      | 15 ---------
>  .../controller/hisilicon,pcie-sas-subctrl.yaml     | 37 ++++++++++++++++++++++
>  2 files changed, 37 insertions(+), 15 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
>  create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
> deleted file mode 100644
> index 43efdaf408f6fe1..000000000000000
> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
> +++ /dev/null
> @@ -1,15 +0,0 @@
> -Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
> -
> -Required properties:
> -- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
> -- reg : Register address and size
> -
> -The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
> -HiP05 or HiP06 Soc to implement some basic configurations.
> -
> -Example:
> -	/* for HiP05 PCIe-SAS sub system */
> -	pcie_sas: system_controller@b0000000 {
> -		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> -		reg = <0xb0000000 0x10000>;
> -	};
> \ No newline at end of file
> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml
> new file mode 100644
> index 000000000000000..8d1341022de587d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml
> @@ -0,0 +1,37 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller
> +
> +maintainers:
> +  - Wei Xu <xuwei5@hisilicon.com>
> +
> +description: |
> +  The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
> +  HiP05 or HiP06 Soc to implement some basic configurations.
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: hisilicon,pcie-sas-subctrl
> +      - const: syscon
> +
> +  reg:
> +    description: Register address and size
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +examples:
> +  - |
> +    /* for HiP05 PCIe-SAS sub system */
> +    pcie_sas: system_controller@b0000000 {
> +        compatible = "hisilicon,pcie-sas-subctrl", "syscon";
> +        reg = <0xb0000000 0x10000>;
> +    };
> +...
> \ No newline at end of file

Trivial, but fix that by adding one.

Jonathan
Leizhen (ThunderTown) Sept. 28, 2020, 11:16 a.m. UTC | #2 
On 2020/9/28 17:46, Jonathan Cameron wrote:
> On Sun, 27 Sep 2020 14:21:18 +0800
> Zhen Lei <thunder.leizhen@huawei.com> wrote:
> 
>> Convert the Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller binding
>> to DT schema format using json-schema.
>>
>> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
> 
> One small thing inline to fix.
> 
> Jonathan
> 
>> ---
>>  .../controller/hisilicon,pcie-sas-subctrl.txt      | 15 ---------
>>  .../controller/hisilicon,pcie-sas-subctrl.yaml     | 37 ++++++++++++++++++++++
>>  2 files changed, 37 insertions(+), 15 deletions(-)
>>  delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
>>  create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
>> deleted file mode 100644
>> index 43efdaf408f6fe1..000000000000000
>> --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
>> +++ /dev/null
>> @@ -1,15 +0,0 @@
>> -Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
>> -
>> -Required properties:
>> -- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
>> -- reg : Register address and size
>> -
>> -The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
>> -HiP05 or HiP06 Soc to implement some basic configurations.
>> -
>> -Example:
>> -	/* for HiP05 PCIe-SAS sub system */
>> -	pcie_sas: system_controller@b0000000 {
>> -		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
>> -		reg = <0xb0000000 0x10000>;
>> -	};
>> \ No newline at end of file
>> diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml
>> new file mode 100644
>> index 000000000000000..8d1341022de587d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml
>> @@ -0,0 +1,37 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller
>> +
>> +maintainers:
>> +  - Wei Xu <xuwei5@hisilicon.com>
>> +
>> +description: |
>> +  The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
>> +  HiP05 or HiP06 Soc to implement some basic configurations.
>> +
>> +properties:
>> +  compatible:
>> +    items:
>> +      - const: hisilicon,pcie-sas-subctrl
>> +      - const: syscon
>> +
>> +  reg:
>> +    description: Register address and size
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +
>> +examples:
>> +  - |
>> +    /* for HiP05 PCIe-SAS sub system */
>> +    pcie_sas: system_controller@b0000000 {
>> +        compatible = "hisilicon,pcie-sas-subctrl", "syscon";
>> +        reg = <0xb0000000 0x10000>;
>> +    };
>> +...
>> \ No newline at end of file
> 
> Trivial, but fix that by adding one.

I think I can directly delete "\ No newline at end of file".
I looked at some files and all of them did not add blank lines at the end.
Whether there is a blank line at enf of file or not, the scripts/checkpatch
does not report any warning.

> 
> Jonathan
> 
> 
> 
> .
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
deleted file mode 100644
index 43efdaf408f6fe1..000000000000000
--- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt
+++ /dev/null
@@ -1,15 +0,0 @@ 
-Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
-
-Required properties:
-- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
-- reg : Register address and size
-
-The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
-HiP05 or HiP06 Soc to implement some basic configurations.
-
-Example:
-	/* for HiP05 PCIe-SAS sub system */
-	pcie_sas: system_controller@b0000000 {
-		compatible = "hisilicon,pcie-sas-subctrl", "syscon";
-		reg = <0xb0000000 0x10000>;
-	};
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml
new file mode 100644
index 000000000000000..8d1341022de587d
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml
@@ -0,0 +1,37 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller
+
+maintainers:
+  - Wei Xu <xuwei5@hisilicon.com>
+
+description: |
+  The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
+  HiP05 or HiP06 Soc to implement some basic configurations.
+
+properties:
+  compatible:
+    items:
+      - const: hisilicon,pcie-sas-subctrl
+      - const: syscon
+
+  reg:
+    description: Register address and size
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    /* for HiP05 PCIe-SAS sub system */
+    pcie_sas: system_controller@b0000000 {
+        compatible = "hisilicon,pcie-sas-subctrl", "syscon";
+        reg = <0xb0000000 0x10000>;
+    };
+...
\ No newline at end of file