[v3,00/15] Tegra XHCI controller ELPG support

Message

JC Kuo Sept. 9, 2020, 8:10 a.m. UTC

Tegra XHCI controler can be placed in ELPG (Engine Level PowerGated)
state for power saving when all of the connected USB devices are in
suspended state. This patch series includes clk, phy and pmc changes
that are required for properly place controller in ELPG and bring
controller out of ELPG.

JC Kuo (15):
  clk: tegra: Add PLLE HW power sequencer control
  clk: tegra: Don't enable PLLE HW sequencer at init
  phy: tegra: xusb: Move usb3 port init for Tegra210
  phy: tegra: xusb: tegra210: Do not reset UPHY PLL
  phy: tegra: xusb: Rearrange UPHY init on Tegra210
  phy: tegra: xusb: Add Tegra210 lane_iddq operation
  phy: tegra: xusb: Add sleepwalk and suspend/resume
  soc/tegra: pmc: Provide usb sleepwalk register map
  arm64: tegra210: XUSB PADCTL add "nvidia,pmc" prop
  phy: tegra: xusb: Add wake/sleepwalk for Tegra210
  phy: tegra: xusb: Tegra210 host mode VBUS control
  phy: tegra: xusb: Add wake/sleepwalk for Tegra186
  arm64: tegra210/tegra186/tegra194: XUSB PADCTL irq
  usb: host: xhci-tegra: Unlink power domain devices
  xhci: tegra: Enable ELPG for runtime/system PM

 arch/arm64/boot/dts/nvidia/tegra186.dtsi |    1 +
 arch/arm64/boot/dts/nvidia/tegra194.dtsi |    1 +
 arch/arm64/boot/dts/nvidia/tegra210.dtsi |    2 +
 drivers/clk/tegra/clk-pll.c              |   12 -
 drivers/clk/tegra/clk-tegra210.c         |   51 +
 drivers/phy/tegra/xusb-tegra186.c        |  626 +++++++
 drivers/phy/tegra/xusb-tegra210.c        | 1968 +++++++++++++++++-----
 drivers/phy/tegra/xusb.c                 |   81 +-
 drivers/phy/tegra/xusb.h                 |   21 +-
 drivers/soc/tegra/pmc.c                  |   95 ++
 drivers/usb/host/xhci-tegra.c            |  572 +++++--
 include/linux/clk/tegra.h                |    2 +
 include/linux/phy/tegra/xusb.h           |    8 +
 13 files changed, 2907 insertions(+), 533 deletions(-)

Comments

Thierry Reding Sept. 28, 2020, 12:54 p.m. UTC | #1

On Wed, Sep 09, 2020 at 04:10:26PM +0800, JC Kuo wrote:
> Tegra XHCI controler can be placed in ELPG (Engine Level PowerGated)
> state for power saving when all of the connected USB devices are in
> suspended state. This patch series includes clk, phy and pmc changes
> that are required for properly place controller in ELPG and bring
> controller out of ELPG.
> 
> JC Kuo (15):
>   clk: tegra: Add PLLE HW power sequencer control
>   clk: tegra: Don't enable PLLE HW sequencer at init

Is it safe to apply this second patch before the others have applied?
Since we now need to explicitly enable the HW sequencer, it won't be
enabled before the corresponding patch does that. So applying patch 2
before the others sounds like it would break existing users of the HW
sequencer.

Thierry

JC Kuo Oct. 14, 2020, 2:26 a.m. UTC | #2

Yes, it's safe to apply "clk: tegra: Don't enable PLLE HW sequencer at init"
before the others have applied. Disabling PLLE hardware power sequencer will not
cause any functionality problem to XUSB/PCIE/SATA. The only thing changed is
PLLE won't be powered off by hardware when all clients are in low power state,
i.e., software has to explicitly power off PLLE.

Thanks for review.
JC

On 9/28/20 8:54 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:26PM +0800, JC Kuo wrote:
>> Tegra XHCI controler can be placed in ELPG (Engine Level PowerGated)
>> state for power saving when all of the connected USB devices are in
>> suspended state. This patch series includes clk, phy and pmc changes
>> that are required for properly place controller in ELPG and bring
>> controller out of ELPG.
>>
>> JC Kuo (15):
>>   clk: tegra: Add PLLE HW power sequencer control
>>   clk: tegra: Don't enable PLLE HW sequencer at init
> 
> Is it safe to apply this second patch before the others have applied?
> Since we now need to explicitly enable the HW sequencer, it won't be
> enabled before the corresponding patch does that. So applying patch 2
> before the others sounds like it would break existing users of the HW
> sequencer.
> 
> Thierry
>