| Message ID | 20200929134642.26561-2-crystal.guo@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | introduce TI reset controller for MT8192 SoC | expand |
On Tue, 29 Sep 2020 21:46:40 +0800, Crystal Guo wrote: > Add a YAML documentation for Mediatek, which uses ti reset-controller > driver directly. The TI reset controller provides a common reset management, > and is suitable for Mediatek SoCs. > > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> > --- > .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++ > 1 file changed, 51 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml > My bot found errors running 'make dt_binding_check' on your patch: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.example.dt.yaml: example-0: infracfg@10001000:reg:0: [0, 268439552, 0, 4096] is too long From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/reg.yaml See https://patchwork.ozlabs.org/patch/1373428 If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure dt-schema is up to date: pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade Please check and re-submit.
On Tue, 2020-09-29 at 23:48 +0800, Rob Herring wrote: > On Tue, 29 Sep 2020 21:46:40 +0800, Crystal Guo wrote: > > Add a YAML documentation for Mediatek, which uses ti reset-controller > > driver directly. The TI reset controller provides a common reset management, > > and is suitable for Mediatek SoCs. > > > > Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> > > --- > > .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++ > > 1 file changed, 51 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml > > > > > My bot found errors running 'make dt_binding_check' on your patch: > > /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.example.dt.yaml: example-0: infracfg@10001000:reg:0: [0, 268439552, 0, 4096] is too long > From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/reg.yaml > > > See https://patchwork.ozlabs.org/patch/1373428 > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure dt-schema is up to date: > > pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade > > Please check and re-submit. > Thanks for your remind, re-submit at: https://patchwork.kernel.org/patch/11807721/
diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml new file mode 100644 index 000000000000..dab630e95a0d --- /dev/null +++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek Reset Controller + +maintainers: + - Crystal Guo <crystal.guo@mediatek.com> + +description: + The bindings describe the reset-controller for Mediatek SoCs, + which is based on TI reset controller. For more detail, please + visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. + +properties: + compatible: + const: mediatek,syscon-reset + + '#reset-cells': + const: 1 + + mediatek,reset-bits: + description: > + Contains the reset control register information, please refer to + Documentation/devicetree/bindings/reset/ti-syscon-reset.txt. + +required: + - compatible + - '#reset-cells' + - mediatek,reset-bits + +additionalProperties: false + +examples: + - | + #include <dt-bindings/reset/ti-syscon.h> + infracfg: infracfg@10001000 { + compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + + infracfg_rst: reset-controller { + compatible = "mediatek,syscon-reset"; + #reset-cells = <1>; + mediatek,reset-bits = < + 0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) + >; + }; + };
Add a YAML documentation for Mediatek, which uses ti reset-controller driver directly. The TI reset controller provides a common reset management, and is suitable for Mediatek SoCs. Signed-off-by: Crystal Guo <crystal.guo@mediatek.com> --- .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml