[v5,0/6] RISC-V Pointer Masking implementation

Message

Alexey Baturo Oct. 22, 2020, 7:43 a.m. UTC

Hi,

Addressing Alistair comment: J-ext enabling patch is now the last one in the series.

Thanks

Alexey Baturo (5):
  [RISCV_PM] Add J-extension into RISC-V
  [RISCV_PM] Support CSRs required for RISC-V PM extension except for
    ones in hypervisor mode
  [RISCV_PM] Print new PM CSRs in QEMU logs
  [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
    instructions
  [RISCV_PM] Allow experimental J-ext to be turned on

Anatoly Parshintsev (1):
  [RISCV_PM] Implement address masking functions required for RISC-V
    Pointer Masking extension

 target/riscv/cpu.c                      |  30 +++
 target/riscv/cpu.h                      |  33 +++
 target/riscv/cpu_bits.h                 |  66 ++++++
 target/riscv/csr.c                      | 271 ++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rva.c.inc |   3 +
 target/riscv/insn_trans/trans_rvd.c.inc |   2 +
 target/riscv/insn_trans/trans_rvf.c.inc |   2 +
 target/riscv/insn_trans/trans_rvi.c.inc |   2 +
 target/riscv/translate.c                |  44 ++++
 9 files changed, 453 insertions(+)

Comments

[e-mail] Oct. 22, 2020, 7:57 a.m. UTC | #1

Patchew URL: https://patchew.org/QEMU/[e-mail]/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: [e-mail]
Subject: [PATCH v5 0/6] RISC-V Pointer Masking implementation

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/[e-mail] -> patchew/[e-mail]
 - [tag update]      patchew/[e-mail] -> patchew/[e-mail]
 * [new tag]         patchew/[e-mail] -> patchew/[e-mail]
Switched to a new branch 'test'
047d80b Allow experimental J-ext to be turned on
2f7a895 Implement address masking functions required for RISC-V Pointer Masking extension
68d35c2 Support pointer masking for RISC-V for i/c/f/d/a types of instructions
19b617f Print new PM CSRs in QEMU logs
97bfef1 Support CSRs required for RISC-V PM extension except for ones in hypervisor mode
a02813c Add J-extension into RISC-V

=== OUTPUT BEGIN ===
1/6 Checking commit a02813c05dac (Add J-extension into RISC-V)
ERROR: Missing Signed-off-by: line(s)

total: 1 errors, 0 warnings, 21 lines checked

Patch 1/6 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

2/6 Checking commit 97bfef184299 (Support CSRs required for RISC-V PM extension except for ones in hypervisor mode)
3/6 Checking commit 19b617fc2d40 (Print new PM CSRs in QEMU logs)
4/6 Checking commit 68d35c24e0d4 (Support pointer masking for RISC-V for i/c/f/d/a types of instructions)
5/6 Checking commit 2f7a895949b8 (Implement address masking functions required for RISC-V Pointer Masking extension)
6/6 Checking commit 047d80ba64a4 (Allow experimental J-ext to be turned on)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/[e-mail]/testing.checkpatch/?type=message.
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