| Message ID | 20201023091225.224-6-jiangyifei@huawei.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Support RISC-V migration | expand |
On Fri, Oct 23, 2020 at 2:18 AM Yifei Jiang <jiangyifei@huawei.com> wrote: > > In the case of supporting V extension, add V extension description > to vmstate_riscv_cpu. > > Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> > Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/machine.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/target/riscv/machine.c b/target/riscv/machine.c > index ae60050898..44d4015bd6 100644 > --- a/target/riscv/machine.c > +++ b/target/riscv/machine.c > @@ -76,6 +76,30 @@ static bool hyper_needed(void *opaque) > return riscv_has_ext(env, RVH); > } > > +static bool vector_needed(void *opaque) > +{ > + RISCVCPU *cpu = opaque; > + CPURISCVState *env = &cpu->env; > + > + return riscv_has_ext(env, RVV); > +} > + > +static const VMStateDescription vmstate_vector = { > + .name = "cpu/vector", > + .version_id = 1, > + .minimum_version_id = 1, > + .needed = vector_needed, > + .fields = (VMStateField[]) { > + VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64), > + VMSTATE_UINTTL(env.vxrm, RISCVCPU), > + VMSTATE_UINTTL(env.vxsat, RISCVCPU), > + VMSTATE_UINTTL(env.vl, RISCVCPU), > + VMSTATE_UINTTL(env.vstart, RISCVCPU), > + VMSTATE_UINTTL(env.vtype, RISCVCPU), > + VMSTATE_END_OF_LIST() > + } > +}; > + > static const VMStateDescription vmstate_hyper = { > .name = "cpu/hyper", > .version_id = 1, > @@ -166,6 +190,7 @@ const VMStateDescription vmstate_riscv_cpu = { > .subsections = (const VMStateDescription * []) { > &vmstate_pmp, > &vmstate_hyper, > + &vmstate_vector, > NULL > } > }; > -- > 2.19.1 > >
diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ae60050898..44d4015bd6 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -76,6 +76,30 @@ static bool hyper_needed(void *opaque) return riscv_has_ext(env, RVH); } +static bool vector_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + return riscv_has_ext(env, RVV); +} + +static const VMStateDescription vmstate_vector = { + .name = "cpu/vector", + .version_id = 1, + .minimum_version_id = 1, + .needed = vector_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64), + VMSTATE_UINTTL(env.vxrm, RISCVCPU), + VMSTATE_UINTTL(env.vxsat, RISCVCPU), + VMSTATE_UINTTL(env.vl, RISCVCPU), + VMSTATE_UINTTL(env.vstart, RISCVCPU), + VMSTATE_UINTTL(env.vtype, RISCVCPU), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_hyper = { .name = "cpu/hyper", .version_id = 1, @@ -166,6 +190,7 @@ const VMStateDescription vmstate_riscv_cpu = { .subsections = (const VMStateDescription * []) { &vmstate_pmp, &vmstate_hyper, + &vmstate_vector, NULL } };