| Message ID | 20200930155006.535712-11-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | i.MX8MM power domain support | expand |
On 9/30/20 5:50 PM, Lucas Stach wrote: > This adds the DT nodes to describe the power domains available on the > i.MX8MM. Things are a bit more complex compared to other GPCv2 power > domain setups, as there is now a hierarchy of domains where complete > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also > fine granular gating within those subsystems is possible. > > Note that this is still incomplete, as both VPU and DISP domains are > missing their reset clocks. Those aren't directly sourced from the CCM, > but have another level of clock gating in the BLKCTL of those domains, > which needs a separate driver. I already have a basic draft of that BLK_CTL driver for MX8MM based on work from Abel, so if we can agree the BLK_CTL is the way forward, I can post that.
On Wed, Sep 30, 2020 at 05:50:05PM +0200, Lucas Stach wrote: > This adds the DT nodes to describe the power domains available on the > i.MX8MM. Things are a bit more complex compared to other GPCv2 power > domain setups, as there is now a hierarchy of domains where complete > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also > fine granular gating within those subsystems is possible. > > Note that this is still incomplete, as both VPU and DISP domains are > missing their reset clocks. Those aren't directly sourced from the CCM, > but have another level of clock gating in the BLKCTL of those domains, > which needs a separate driver. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 +++++++++++++++++++++++ > 1 file changed, 57 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 76f040e4be5e..a841fb2d0458 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -4,6 +4,8 @@ > */ > > #include <dt-bindings/clock/imx8mm-clock.h> > +#include <dt-bindings/power/imx8mm-power.h> > +#include <dt-bindings/reset/imx8mq-reset.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/input/input.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > @@ -547,6 +549,61 @@ > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > #reset-cells = <1>; > }; > + > + gpc: gpc@303a0000 { > + compatible = "fsl,imx8mm-gpc"; > + reg = <0x303a0000 0x10000>; > + interrupt-parent = <&gic>; > + interrupt-controller; This does not validate against your GPC dtschema. Please add DTS which passes own schema from day one (except existing issues). Best regards, Krzysztof
On Wed, Sep 30, 2020 at 10:55 AM Lucas Stach <l.stach@pengutronix.de> wrote: > > This adds the DT nodes to describe the power domains available on the > i.MX8MM. Things are a bit more complex compared to other GPCv2 power > domain setups, as there is now a hierarchy of domains where complete > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also > fine granular gating within those subsystems is possible. > > Note that this is still incomplete, as both VPU and DISP domains are > missing their reset clocks. Those aren't directly sourced from the CCM, > but have another level of clock gating in the BLKCTL of those domains, > which needs a separate driver. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 +++++++++++++++++++++++ > 1 file changed, 57 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 76f040e4be5e..a841fb2d0458 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -4,6 +4,8 @@ > */ > > #include <dt-bindings/clock/imx8mm-clock.h> > +#include <dt-bindings/power/imx8mm-power.h> > +#include <dt-bindings/reset/imx8mq-reset.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/input/input.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > @@ -547,6 +549,61 @@ > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > #reset-cells = <1>; > }; > + > + gpc: gpc@303a0000 { > + compatible = "fsl,imx8mm-gpc"; > + reg = <0x303a0000 0x10000>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + #interrupt-cells = <3>; Does this need an interrupt index within the GIC? possibly something like: interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; > + > + pgc { > + #address-cells = <1>; > + #size-cells = <0>; > + > + pgc_hsiomix: power-domain@0 { > + #power-domain-cells = <0>; > + reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>; > + clocks = <&clk IMX8MM_CLK_USB_BUS>; > + }; > + > + pgc_pcie: power-domain@1 { > + #power-domain-cells = <0>; > + reg = <IMX8MM_POWER_DOMAIN_PCIE>; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_otg1: power-domain@2 { > + #power-domain-cells = <0>; > + reg = <IMX8MM_POWER_DOMAIN_OTG1>; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_otg2: power-domain@3 { > + #power-domain-cells = <0>; > + reg = <IMX8MM_POWER_DOMAIN_OTG2>; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_gpumix: power-domain@4 { > + #power-domain-cells = <0>; > + reg = <IMX8MM_POWER_DOMAIN_GPUMIX>; > + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MM_CLK_GPU_AHB>; > + }; > + > + pgc_gpu: power-domain@5 { > + #power-domain-cells = <0>; > + reg = <IMX8MM_POWER_DOMAIN_GPU>; > + clocks = <&clk IMX8MM_CLK_GPU_AHB>, > + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MM_CLK_GPU2D_ROOT>, > + <&clk IMX8MM_CLK_GPU3D_ROOT>; > + resets = <&src IMX8MQ_RESET_GPU_RESET>; > + power-domains = <&pgc_gpumix>; > + }; > + }; > + }; > }; > > aips2: bus@30400000 { > -- > 2.20.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> -----Original Message----- > From: Adam Ford [mailto:aford173@gmail.com] > Sent: Friday, October 23, 2020 9:22 PM > To: Lucas Stach <l.stach@pengutronix.de> > Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring <robh+dt@kernel.org>; > Marek Vasut <marex@denx.de>; devicetree <devicetree@vger.kernel.org>; > Frieder Schrempf <frieder.schrempf@kontron.de>; > patchwork-lst@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>; Sascha > Hauer <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>; > arm-soc <linux-arm-kernel@lists.infradead.org> > Subject: Re: [PATCH 10/11] arm64: dts: imx8mm: add GPC node and power > domains > > On Wed, Sep 30, 2020 at 10:55 AM Lucas Stach <l.stach@pengutronix.de> > wrote: > > > > This adds the DT nodes to describe the power domains available on the > > i.MX8MM. Things are a bit more complex compared to other GPCv2 power > > domain setups, as there is now a hierarchy of domains where complete > > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also fine > > granular gating within those subsystems is possible. > > > > Note that this is still incomplete, as both VPU and DISP domains are > > missing their reset clocks. Those aren't directly sourced from the > > CCM, but have another level of clock gating in the BLKCTL of those > > domains, which needs a separate driver. > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > --- > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 > > +++++++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > index 76f040e4be5e..a841fb2d0458 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > @@ -4,6 +4,8 @@ > > */ > > > > #include <dt-bindings/clock/imx8mm-clock.h> > > +#include <dt-bindings/power/imx8mm-power.h> > > +#include <dt-bindings/reset/imx8mq-reset.h> > > #include <dt-bindings/gpio/gpio.h> > > #include <dt-bindings/input/input.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > @@ -547,6 +549,61 @@ > > interrupts = <GIC_SPI 89 > IRQ_TYPE_LEVEL_HIGH>; > > #reset-cells = <1>; > > }; > > + > > + gpc: gpc@303a0000 { > > + compatible = "fsl,imx8mm-gpc"; > > + reg = <0x303a0000 0x10000>; > > + interrupt-parent = <&gic>; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > Does this need an interrupt index within the GIC? > possibly something like: interrupts = <GIC_SPI 87 > IRQ_TYPE_LEVEL_HIGH>; For imx8m, except imx8mq, we don’t use gpc as interrupt controller anymore, the propterty for gic controller etc are redundant, I think BR Jacky Bai > > > > + > > + pgc { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + pgc_hsiomix: > power-domain@0 { > > + > #power-domain-cells = <0>; > > + reg = > <IMX8MM_POWER_DOMAIN_HSIOMIX>; > > + clocks = <&clk > IMX8MM_CLK_USB_BUS>; > > + }; > > + > > + pgc_pcie: > power-domain@1 { > > + > #power-domain-cells = <0>; > > + reg = > <IMX8MM_POWER_DOMAIN_PCIE>; > > + power-domains > = <&pgc_hsiomix>; > > + }; > > + > > + pgc_otg1: > power-domain@2 { > > + > #power-domain-cells = <0>; > > + reg = > <IMX8MM_POWER_DOMAIN_OTG1>; > > + power-domains > = <&pgc_hsiomix>; > > + }; > > + > > + pgc_otg2: > power-domain@3 { > > + > #power-domain-cells = <0>; > > + reg = > <IMX8MM_POWER_DOMAIN_OTG2>; > > + power-domains > = <&pgc_hsiomix>; > > + }; > > + > > + pgc_gpumix: > power-domain@4 { > > + > #power-domain-cells = <0>; > > + reg = > <IMX8MM_POWER_DOMAIN_GPUMIX>; > > + clocks = <&clk > IMX8MM_CLK_GPU_BUS_ROOT>, > > + > <&clk IMX8MM_CLK_GPU_AHB>; > > + }; > > + > > + pgc_gpu: > power-domain@5 { > > + > #power-domain-cells = <0>; > > + reg = > <IMX8MM_POWER_DOMAIN_GPU>; > > + clocks = <&clk > IMX8MM_CLK_GPU_AHB>, > > + > <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > > + > <&clk IMX8MM_CLK_GPU2D_ROOT>, > > + > <&clk IMX8MM_CLK_GPU3D_ROOT>; > > + resets = <&src > IMX8MQ_RESET_GPU_RESET>; > > + power-domains > = <&pgc_gpumix>; > > + }; > > + }; > > + }; > > }; > > > > aips2: bus@30400000 { > > -- > > 2.20.1 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists > > .infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&data=04% > 7C0 > > > 1%7Cping.bai%40nxp.com%7C412f29610c79470d12c408d87756b072%7C68 > 6ea1d3bc > > > 2b4c6fa92cd99c5c301635%7C0%7C0%7C637390561501622327%7CUnknow > n%7CTWFpbG > > > Zsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6 > Mn0% > > > 3D%7C1000&sdata=AazKzk1Tl6LI1hLYGW1xQ%2FEYc8Ad6vk0aBdkJxwu > w3A%3D&a > > mp;reserved=0
On 20-09-30 17:50:05, Lucas Stach wrote: > This adds the DT nodes to describe the power domains available on the > i.MX8MM. Things are a bit more complex compared to other GPCv2 power > domain setups, as there is now a hierarchy of domains where complete > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also > fine granular gating within those subsystems is possible. > > Note that this is still incomplete, as both VPU and DISP domains are > missing their reset clocks. Those aren't directly sourced from the CCM, > but have another level of clock gating in the BLKCTL of those domains, > which needs a separate driver. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 +++++++++++++++++++++++ > 1 file changed, 57 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 76f040e4be5e..a841fb2d0458 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -4,6 +4,8 @@ > */ > > #include <dt-bindings/clock/imx8mm-clock.h> > +#include <dt-bindings/power/imx8mm-power.h> > +#include <dt-bindings/reset/imx8mq-reset.h> Needs to be imx8mm-reset.h, as in 8MM, not 8MQ. > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/input/input.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > @@ -547,6 +549,61 @@ > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > #reset-cells = <1>; > }; > + > + gpc: gpc@303a0000 { > + compatible = "fsl,imx8mm-gpc"; > + reg = <0x303a0000 0x10000>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + #interrupt-cells = <3>; > + > + pgc { > + #address-cells = <1>; > + #size-cells = <0>; > + > + pgc_hsiomix: power-domain@0 { > + #power-domain-cells = <0>; > + reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>; > + clocks = <&clk IMX8MM_CLK_USB_BUS>; > + }; > + > + pgc_pcie: power-domain@1 { > + #power-domain-cells = <0>; > + reg = <IMX8MM_POWER_DOMAIN_PCIE>; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_otg1: power-domain@2 { > + #power-domain-cells = <0>; > + reg = <IMX8MM_POWER_DOMAIN_OTG1>; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_otg2: power-domain@3 { > + #power-domain-cells = <0>; > + reg = <IMX8MM_POWER_DOMAIN_OTG2>; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_gpumix: power-domain@4 { > + #power-domain-cells = <0>; > + reg = <IMX8MM_POWER_DOMAIN_GPUMIX>; > + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MM_CLK_GPU_AHB>; > + }; > + > + pgc_gpu: power-domain@5 { > + #power-domain-cells = <0>; > + reg = <IMX8MM_POWER_DOMAIN_GPU>; > + clocks = <&clk IMX8MM_CLK_GPU_AHB>, > + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MM_CLK_GPU2D_ROOT>, > + <&clk IMX8MM_CLK_GPU3D_ROOT>; > + resets = <&src IMX8MQ_RESET_GPU_RESET>; > + power-domains = <&pgc_gpumix>; > + }; > + }; > + }; > }; > > aips2: bus@30400000 { > -- > 2.20.1 >
On 20-10-26 12:56:22, Abel Vesa wrote: > On 20-09-30 17:50:05, Lucas Stach wrote: > > This adds the DT nodes to describe the power domains available on the > > i.MX8MM. Things are a bit more complex compared to other GPCv2 power > > domain setups, as there is now a hierarchy of domains where complete > > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also > > fine granular gating within those subsystems is possible. > > > > Note that this is still incomplete, as both VPU and DISP domains are > > missing their reset clocks. Those aren't directly sourced from the CCM, > > but have another level of clock gating in the BLKCTL of those domains, > > which needs a separate driver. > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > --- > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 +++++++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > index 76f040e4be5e..a841fb2d0458 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > @@ -4,6 +4,8 @@ > > */ > > > > #include <dt-bindings/clock/imx8mm-clock.h> > > +#include <dt-bindings/power/imx8mm-power.h> > > +#include <dt-bindings/reset/imx8mq-reset.h> > > Needs to be imx8mm-reset.h, as in 8MM, not 8MQ. > Actually, now I see what you've done here. You want to use the IMX8MQ_RESET_GPU_RESET. But I think we should avoid having reset IDs shared between i.MX8M platforms. I'll try to find another way around this myself. > > #include <dt-bindings/gpio/gpio.h> > > #include <dt-bindings/input/input.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > @@ -547,6 +549,61 @@ > > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > > #reset-cells = <1>; > > }; > > + > > + gpc: gpc@303a0000 { > > + compatible = "fsl,imx8mm-gpc"; > > + reg = <0x303a0000 0x10000>; > > + interrupt-parent = <&gic>; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + > > + pgc { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + pgc_hsiomix: power-domain@0 { > > + #power-domain-cells = <0>; > > + reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>; > > + clocks = <&clk IMX8MM_CLK_USB_BUS>; > > + }; > > + > > + pgc_pcie: power-domain@1 { > > + #power-domain-cells = <0>; > > + reg = <IMX8MM_POWER_DOMAIN_PCIE>; > > + power-domains = <&pgc_hsiomix>; > > + }; > > + > > + pgc_otg1: power-domain@2 { > > + #power-domain-cells = <0>; > > + reg = <IMX8MM_POWER_DOMAIN_OTG1>; > > + power-domains = <&pgc_hsiomix>; > > + }; > > + > > + pgc_otg2: power-domain@3 { > > + #power-domain-cells = <0>; > > + reg = <IMX8MM_POWER_DOMAIN_OTG2>; > > + power-domains = <&pgc_hsiomix>; > > + }; > > + > > + pgc_gpumix: power-domain@4 { > > + #power-domain-cells = <0>; > > + reg = <IMX8MM_POWER_DOMAIN_GPUMIX>; > > + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > > + <&clk IMX8MM_CLK_GPU_AHB>; > > + }; > > + > > + pgc_gpu: power-domain@5 { > > + #power-domain-cells = <0>; > > + reg = <IMX8MM_POWER_DOMAIN_GPU>; > > + clocks = <&clk IMX8MM_CLK_GPU_AHB>, > > + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > > + <&clk IMX8MM_CLK_GPU2D_ROOT>, > > + <&clk IMX8MM_CLK_GPU3D_ROOT>; > > + resets = <&src IMX8MQ_RESET_GPU_RESET>; > > + power-domains = <&pgc_gpumix>; > > + }; > > + }; > > + }; > > }; > > > > aips2: bus@30400000 { > > -- > > 2.20.1 > >
Hi Abel, Am Montag, den 26.10.2020, 12:56 +0200 schrieb Abel Vesa: > On 20-09-30 17:50:05, Lucas Stach wrote: > > This adds the DT nodes to describe the power domains available on the > > i.MX8MM. Things are a bit more complex compared to other GPCv2 power > > domain setups, as there is now a hierarchy of domains where complete > > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also > > fine granular gating within those subsystems is possible. > > > > Note that this is still incomplete, as both VPU and DISP domains are > > missing their reset clocks. Those aren't directly sourced from the CCM, > > but have another level of clock gating in the BLKCTL of those domains, > > which needs a separate driver. > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > --- > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 +++++++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > index 76f040e4be5e..a841fb2d0458 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > @@ -4,6 +4,8 @@ > > */ > > > > #include <dt-bindings/clock/imx8mm-clock.h> > > +#include <dt-bindings/power/imx8mm-power.h> > > +#include <dt-bindings/reset/imx8mq-reset.h> > > Needs to be imx8mm-reset.h, as in 8MM, not 8MQ. It's confusing, but the reset driver uses the same defines for i.MX8MM. Comments in the imx8mq-reset.h file even specify which resets aren't supported on i.MX8MM. Regards, Lucas > > #include <dt-bindings/gpio/gpio.h> > > #include <dt-bindings/input/input.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > @@ -547,6 +549,61 @@ > > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > > #reset-cells = <1>; > > }; > > + > > + gpc: gpc@303a0000 { > > + compatible = "fsl,imx8mm-gpc"; > > + reg = <0x303a0000 0x10000>; > > + interrupt-parent = <&gic>; > > + interrupt-controller; > > + #interrupt-cells = <3>; > > + > > + pgc { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + pgc_hsiomix: power-domain@0 { > > + #power-domain-cells = <0>; > > + reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>; > > + clocks = <&clk IMX8MM_CLK_USB_BUS>; > > + }; > > + > > + pgc_pcie: power-domain@1 { > > + #power-domain-cells = <0>; > > + reg = <IMX8MM_POWER_DOMAIN_PCIE>; > > + power-domains = <&pgc_hsiomix>; > > + }; > > + > > + pgc_otg1: power-domain@2 { > > + #power-domain-cells = <0>; > > + reg = <IMX8MM_POWER_DOMAIN_OTG1>; > > + power-domains = <&pgc_hsiomix>; > > + }; > > + > > + pgc_otg2: power-domain@3 { > > + #power-domain-cells = <0>; > > + reg = <IMX8MM_POWER_DOMAIN_OTG2>; > > + power-domains = <&pgc_hsiomix>; > > + }; > > + > > + pgc_gpumix: power-domain@4 { > > + #power-domain-cells = <0>; > > + reg = <IMX8MM_POWER_DOMAIN_GPUMIX>; > > + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > > + <&clk IMX8MM_CLK_GPU_AHB>; > > + }; > > + > > + pgc_gpu: power-domain@5 { > > + #power-domain-cells = <0>; > > + reg = <IMX8MM_POWER_DOMAIN_GPU>; > > + clocks = <&clk IMX8MM_CLK_GPU_AHB>, > > + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > > + <&clk IMX8MM_CLK_GPU2D_ROOT>, > > + <&clk IMX8MM_CLK_GPU3D_ROOT>; > > + resets = <&src IMX8MQ_RESET_GPU_RESET>; > > + power-domains = <&pgc_gpumix>; > > + }; > > + }; > > + }; > > }; > > > > aips2: bus@30400000 { > > -- > > 2.20.1 > >
On Mon, Oct 26, 2020 at 6:07 AM Abel Vesa <abel.vesa@nxp.com> wrote: > > On 20-10-26 12:56:22, Abel Vesa wrote: > > On 20-09-30 17:50:05, Lucas Stach wrote: > > > This adds the DT nodes to describe the power domains available on the > > > i.MX8MM. Things are a bit more complex compared to other GPCv2 power > > > domain setups, as there is now a hierarchy of domains where complete > > > subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also > > > fine granular gating within those subsystems is possible. > > > > > > Note that this is still incomplete, as both VPU and DISP domains are > > > missing their reset clocks. Those aren't directly sourced from the CCM, > > > but have another level of clock gating in the BLKCTL of those domains, > > > which needs a separate driver. > > > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > > --- > > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 +++++++++++++++++++++++ > > > 1 file changed, 57 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > > index 76f040e4be5e..a841fb2d0458 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > > > @@ -4,6 +4,8 @@ > > > */ > > > > > > #include <dt-bindings/clock/imx8mm-clock.h> > > > +#include <dt-bindings/power/imx8mm-power.h> > > > +#include <dt-bindings/reset/imx8mq-reset.h> > > > > Needs to be imx8mm-reset.h, as in 8MM, not 8MQ. > > > > Actually, now I see what you've done here. You want to use the IMX8MQ_RESET_GPU_RESET. > > But I think we should avoid having reset IDs shared between i.MX8M platforms. > > I'll try to find another way around this myself. The nano does the same thing as the mini as both appear to be subsets of the i.MX8MQ. I spent a fair amount of time reviewing the SRC driver yesterday. > > > > #include <dt-bindings/gpio/gpio.h> > > > #include <dt-bindings/input/input.h> > > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > > @@ -547,6 +549,61 @@ > > > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > > > #reset-cells = <1>; > > > }; > > > + > > > + gpc: gpc@303a0000 { > > > + compatible = "fsl,imx8mm-gpc"; > > > + reg = <0x303a0000 0x10000>; > > > + interrupt-parent = <&gic>; > > > + interrupt-controller; > > > + #interrupt-cells = <3>; > > > + > > > + pgc { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + pgc_hsiomix: power-domain@0 { > > > + #power-domain-cells = <0>; > > > + reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>; > > > + clocks = <&clk IMX8MM_CLK_USB_BUS>; > > > + }; > > > + > > > + pgc_pcie: power-domain@1 { > > > + #power-domain-cells = <0>; > > > + reg = <IMX8MM_POWER_DOMAIN_PCIE>; > > > + power-domains = <&pgc_hsiomix>; > > > + }; > > > + > > > + pgc_otg1: power-domain@2 { > > > + #power-domain-cells = <0>; > > > + reg = <IMX8MM_POWER_DOMAIN_OTG1>; > > > + power-domains = <&pgc_hsiomix>; > > > + }; > > > + > > > + pgc_otg2: power-domain@3 { > > > + #power-domain-cells = <0>; > > > + reg = <IMX8MM_POWER_DOMAIN_OTG2>; > > > + power-domains = <&pgc_hsiomix>; > > > + }; > > > + > > > + pgc_gpumix: power-domain@4 { > > > + #power-domain-cells = <0>; > > > + reg = <IMX8MM_POWER_DOMAIN_GPUMIX>; > > > + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > > > + <&clk IMX8MM_CLK_GPU_AHB>; > > > + }; > > > + > > > + pgc_gpu: power-domain@5 { > > > + #power-domain-cells = <0>; > > > + reg = <IMX8MM_POWER_DOMAIN_GPU>; > > > + clocks = <&clk IMX8MM_CLK_GPU_AHB>, > > > + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, > > > + <&clk IMX8MM_CLK_GPU2D_ROOT>, > > > + <&clk IMX8MM_CLK_GPU3D_ROOT>; > > > + resets = <&src IMX8MQ_RESET_GPU_RESET>; > > > + power-domains = <&pgc_gpumix>; > > > + }; > > > + }; > > > + }; > > > }; > > > > > > aips2: bus@30400000 { > > > -- > > > 2.20.1 > > > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 76f040e4be5e..a841fb2d0458 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -4,6 +4,8 @@ */ #include <dt-bindings/clock/imx8mm-clock.h> +#include <dt-bindings/power/imx8mm-power.h> +#include <dt-bindings/reset/imx8mq-reset.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -547,6 +549,61 @@ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mm-gpc"; + reg = <0x303a0000 0x10000>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_hsiomix: power-domain@0 { + #power-domain-cells = <0>; + reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>; + clocks = <&clk IMX8MM_CLK_USB_BUS>; + }; + + pgc_pcie: power-domain@1 { + #power-domain-cells = <0>; + reg = <IMX8MM_POWER_DOMAIN_PCIE>; + power-domains = <&pgc_hsiomix>; + }; + + pgc_otg1: power-domain@2 { + #power-domain-cells = <0>; + reg = <IMX8MM_POWER_DOMAIN_OTG1>; + power-domains = <&pgc_hsiomix>; + }; + + pgc_otg2: power-domain@3 { + #power-domain-cells = <0>; + reg = <IMX8MM_POWER_DOMAIN_OTG2>; + power-domains = <&pgc_hsiomix>; + }; + + pgc_gpumix: power-domain@4 { + #power-domain-cells = <0>; + reg = <IMX8MM_POWER_DOMAIN_GPUMIX>; + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>; + }; + + pgc_gpu: power-domain@5 { + #power-domain-cells = <0>; + reg = <IMX8MM_POWER_DOMAIN_GPU>; + clocks = <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>; + resets = <&src IMX8MQ_RESET_GPU_RESET>; + power-domains = <&pgc_gpumix>; + }; + }; + }; }; aips2: bus@30400000 {
This adds the DT nodes to describe the power domains available on the i.MX8MM. Things are a bit more complex compared to other GPCv2 power domain setups, as there is now a hierarchy of domains where complete subsystems (HSIO, GPU, DISPLAY) can be gated as a whole, but also fine granular gating within those subsystems is possible. Note that this is still incomplete, as both VPU and DISP domains are missing their reset clocks. Those aren't directly sourced from the CCM, but have another level of clock gating in the BLKCTL of those domains, which needs a separate driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 +++++++++++++++++++++++ 1 file changed, 57 insertions(+)