diff mbox series

[v6,20/52] ARM: tegra: Correct EMC registers size in Tegra20 device-tree

Message ID 20201025221735.3062-21-digetx@gmail.com (mailing list archive)
State New, archived
Headers show
Series Introduce memory interconnect for NVIDIA Tegra SoCs | expand

Commit Message

Dmitry Osipenko Oct. 25, 2020, 10:17 p.m. UTC 
The Tegra20 EMC registers size should be twice bigger. This patch fixes
the size.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 arch/arm/boot/dts/tegra20.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Krzysztof Kozlowski Oct. 27, 2020, 9:10 a.m. UTC | #1 
On Mon, Oct 26, 2020 at 01:17:03AM +0300, Dmitry Osipenko wrote:
> The Tegra20 EMC registers size should be twice bigger. This patch fixes
> the size.

Don't use "This patch" (this appears here). Better to use:
"Fix the size of ..." or just "The size should be twice bigger" as it is
obvious that you fix it.

https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L151

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof
Dmitry Osipenko Oct. 27, 2020, 8:43 p.m. UTC | #2 
27.10.2020 12:10, Krzysztof Kozlowski пишет:
> On Mon, Oct 26, 2020 at 01:17:03AM +0300, Dmitry Osipenko wrote:
>> The Tegra20 EMC registers size should be twice bigger. This patch fixes
>> the size.
> 
> Don't use "This patch" (this appears here). Better to use:
> "Fix the size of ..." or just "The size should be twice bigger" as it is
> obvious that you fix it.
> 
> https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L151
> 
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Thanks, I wasn't aware that it's a preferred wording style now.
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 72a4211a618f..9347f7789245 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -634,7 +634,7 @@  mc: memory-controller@7000f000 {
 
 	memory-controller@7000f400 {
 		compatible = "nvidia,tegra20-emc";
-		reg = <0x7000f400 0x200>;
+		reg = <0x7000f400 0x400>;
 		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&tegra_car TEGRA20_CLK_EMC>;
 		#address-cells = <1>;