| Message ID | 20201029141159.190621-1-tomi.valkeinen@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: ti: k3-am65: mark dss as dma-coherent | expand |
On 16:11-20201029, Tomi Valkeinen wrote: > DSS is IO coherent on AM65, so we can mark it as such with > 'dma-coherent' property in the DT file. > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Acked-by: Nikhil Devshatwar <nikhil.nd@ti.com> Nikhil D > --- > > Sending separately as requested. > > arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > index 533525229a8d..a0b4a421026f 100644 > --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > @@ -867,6 +867,8 @@ dss: dss@04a00000 { > > status = "disabled"; > > + dma-coherent; > + > dss_ports: ports { > #address-cells = <1>; > #size-cells = <0>; > -- > Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. > Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki >
On 20:11-20201029, Nikhil Devshatwar wrote: > On 16:11-20201029, Tomi Valkeinen wrote: > > DSS is IO coherent on AM65, so we can mark it as such with > > 'dma-coherent' property in the DT file. > > > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> > Acked-by: Nikhil Devshatwar <nikhil.nd@ti.com> > Tomi: Do you need to add Fixes: tag to percolate this to stable? if yes, please comment, makes it easier for me to queue for 5.10 if possible
On 29/10/2020 16:52, Nishanth Menon wrote: > On 20:11-20201029, Nikhil Devshatwar wrote: >> On 16:11-20201029, Tomi Valkeinen wrote: >>> DSS is IO coherent on AM65, so we can mark it as such with >>> 'dma-coherent' property in the DT file. >>> >>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> >> Acked-by: Nikhil Devshatwar <nikhil.nd@ti.com> >> > > Tomi: Do you need to add Fixes: tag to percolate this to stable? if > yes, please comment, makes it easier for me to queue for 5.10 if > possible I don't see this as a fix, but an optimization. Nothing is broken without this. Tomi
On 2020-10-30 14:08, Tomi Valkeinen wrote: > On 29/10/2020 16:52, Nishanth Menon wrote: >> On 20:11-20201029, Nikhil Devshatwar wrote: >>> On 16:11-20201029, Tomi Valkeinen wrote: >>>> DSS is IO coherent on AM65, so we can mark it as such with >>>> 'dma-coherent' property in the DT file. >>>> >>>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> >>> Acked-by: Nikhil Devshatwar <nikhil.nd@ti.com> >>> >> >> Tomi: Do you need to add Fixes: tag to percolate this to stable? if >> yes, please comment, makes it easier for me to queue for 5.10 if >> possible > > I don't see this as a fix, but an optimization. Nothing is broken without this. Note that if the driver doesn't have explicit control over what type of memory access the device makes, that's not necessarily true. If coherent DMA buffers are allocated from regular kernel memory, there's still a cacheable alias kicking around that can be speculatively fetched into a cache somewhere. If the device is genuinely non-coherent, or configured to make non-snooping accesses, then that's not an issue, but it it's hard-wired to make snooping accesses it can start hitting that cached alias and not see subsequent updates to the buffer, since those are written straight to RAM via the non-cacheable mapping. At that point it becomes an actual problem (and it's not just theoretical - we've hit a real-world example of this recently with GPUs on certain Amlogic devices). Robin.
Hi, On 02/11/2020 15:01, Robin Murphy wrote: > On 2020-10-30 14:08, Tomi Valkeinen wrote: >> On 29/10/2020 16:52, Nishanth Menon wrote: >>> On 20:11-20201029, Nikhil Devshatwar wrote: >>>> On 16:11-20201029, Tomi Valkeinen wrote: >>>>> DSS is IO coherent on AM65, so we can mark it as such with >>>>> 'dma-coherent' property in the DT file. >>>>> >>>>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> >>>> Acked-by: Nikhil Devshatwar <nikhil.nd@ti.com> >>>> >>> >>> Tomi: Do you need to add Fixes: tag to percolate this to stable? if >>> yes, please comment, makes it easier for me to queue for 5.10 if >>> possible >> >> I don't see this as a fix, but an optimization. Nothing is broken without this. > > Note that if the driver doesn't have explicit control over what type of memory access the device > makes, that's not necessarily true. > > If coherent DMA buffers are allocated from regular kernel memory, there's still a cacheable alias > kicking around that can be speculatively fetched into a cache somewhere. If the device is genuinely > non-coherent, or configured to make non-snooping accesses, then that's not an issue, but it it's > hard-wired to make snooping accesses it can start hitting that cached alias and not see subsequent > updates to the buffer, since those are written straight to RAM via the non-cacheable mapping. At > that point it becomes an actual problem (and it's not just theoretical - we've hit a real-world > example of this recently with GPUs on certain Amlogic devices). Ok, thanks. I don't know if that the case here, but better safe than sorry. I'll send a new one with appropriate tags. Tomi
On 15:42-20201102, Tomi Valkeinen wrote: > Hi, > > On 02/11/2020 15:01, Robin Murphy wrote: > > On 2020-10-30 14:08, Tomi Valkeinen wrote: > >> On 29/10/2020 16:52, Nishanth Menon wrote: > >>> On 20:11-20201029, Nikhil Devshatwar wrote: > >>>> On 16:11-20201029, Tomi Valkeinen wrote: > >>>>> DSS is IO coherent on AM65, so we can mark it as such with > >>>>> 'dma-coherent' property in the DT file. > >>>>> > >>>>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> > >>>> Acked-by: Nikhil Devshatwar <nikhil.nd@ti.com> > >>>> > >>> > >>> Tomi: Do you need to add Fixes: tag to percolate this to stable? if > >>> yes, please comment, makes it easier for me to queue for 5.10 if > >>> possible > >> > >> I don't see this as a fix, but an optimization. Nothing is broken without this. > > > > Note that if the driver doesn't have explicit control over what type of memory access the device > > makes, that's not necessarily true. > > > > If coherent DMA buffers are allocated from regular kernel memory, there's still a cacheable alias > > kicking around that can be speculatively fetched into a cache somewhere. If the device is genuinely > > non-coherent, or configured to make non-snooping accesses, then that's not an issue, but it it's > > hard-wired to make snooping accesses it can start hitting that cached alias and not see subsequent > > updates to the buffer, since those are written straight to RAM via the non-cacheable mapping. At > > that point it becomes an actual problem (and it's not just theoretical - we've hit a real-world > > example of this recently with GPUs on certain Amlogic devices). > > Ok, thanks. I don't know if that the case here, but better safe than sorry. I'll send a new one with > appropriate tags. Yes - the default AM65 MAT tables do force a snoop into the clusters when using DDR based buffers. Deal with display is when you dont get to see the artifacts unless you are closely monitoring frame by frame and transitions.. which in the middle of all other automatic backend cache operations tends to be rather something easy to miss.. Will let the next rev cook for a few days unless folks have some additional comments..
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 533525229a8d..a0b4a421026f 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -867,6 +867,8 @@ dss: dss@04a00000 { status = "disabled"; + dma-coherent; + dss_ports: ports { #address-cells = <1>; #size-cells = <0>;
DSS is IO coherent on AM65, so we can mark it as such with 'dma-coherent' property in the DT file. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> --- Sending separately as requested. arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 ++ 1 file changed, 2 insertions(+)