Message ID | 1604502407-14352-2-git-send-email-shubhrajyoti.datta@xilinx.com (mailing list archive) |
---|---|
State | Changes Requested, archived |
Headers | show |
Series | clk: clk-wizard: clock-wizard: Driver updates | expand |
On Wed, 04 Nov 2020 20:36:41 +0530, Shubhrajyoti Datta wrote: > Add the devicetree binding for the xilinx clocking wizard. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > --- > v6: > Fix a yaml warning > v7: > Add vendor prefix speed-grade > > .../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: ./Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml:21:7: [warning] wrong indentation: expected 4 but found 6 (indentation) ./Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml:38:7: [warning] wrong indentation: expected 4 but found 6 (indentation) ./Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml:40:5: [error] syntax error: expected <block end>, but found '<block mapping start>' (syntax) dtschema/dtc warnings/errors: Traceback (most recent call last): File "/usr/local/bin/dt-extract-example", line 45, in <module> binding = yaml.load(open(args.yamlfile, encoding='utf-8').read()) File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 343, in load return constructor.get_single_data() File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 111, in get_single_data node = self.composer.get_single_node() File "_ruamel_yaml.pyx", line 706, in _ruamel_yaml.CParser.get_single_node File "_ruamel_yaml.pyx", line 724, in _ruamel_yaml.CParser._compose_document File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node File "_ruamel_yaml.pyx", line 891, in _ruamel_yaml.CParser._compose_mapping_node File "_ruamel_yaml.pyx", line 904, in _ruamel_yaml.CParser._parse_next_event ruamel.yaml.parser.ParserError: while parsing a block mapping in "<unicode string>", line 20, column 3 did not find expected key in "<unicode string>", line 40, column 5 make[1]: *** [Documentation/devicetree/bindings/Makefile:20: Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.example.dts] Error 1 make[1]: *** Deleting file 'Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.example.dts' make[1]: *** Waiting for unfinished jobs.... make[1]: *** [Documentation/devicetree/bindings/Makefile:59: Documentation/devicetree/bindings/processed-schema-examples.json] Error 123 make: *** [Makefile:1364: dt_binding_check] Error 2 See https://patchwork.ozlabs.org/patch/1394053 The base for the patch is generally the last rc1. Any dependencies should be noted. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On Wed, Nov 04, 2020 at 08:36:41PM +0530, Shubhrajyoti Datta wrote: > Add the devicetree binding for the xilinx clocking wizard. > > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > --- > v6: > Fix a yaml warning > v7: > Add vendor prefix speed-grade > > .../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > > diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > new file mode 100644 > index 0000000..a19b9bb > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml > @@ -0,0 +1,65 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx clocking wizard > + > +maintainers: > + - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> > + > +description: | > + The clocking wizard is a soft ip clocking block of Xilinx versal. It > + reads required input clock frequencies from the devicetree and acts as clock > + clock output. > + > +select: false Why? That's one way to make the example pass with your schema... > + > +properties: > + compatible: > + - enum: > + - xlnx,clocking-wizard > + > + "#clock-cells": > + const: 1 > + > + clocks: > + items: > + - description: clock input > + - description: axi clock > + > + clock-names: > + items: > + - const: clk_in1 > + - const: s_axi_aclk > + > + xlnx,speed-grade: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - enum: [1, 2, 3] > + description: > + Speed grade of the device. > + > +required: > + - compatible > + - "#clock-cells" > + - clocks > + - clock-names > + - speed-grade > + > +additionalProperties: false > + > +examples: > + - | > + clock-generator@40040000 { > + #clock-cells = <1>; > + reg = <0x40040000 0x1000>; > + compatible = "xlnx,clocking-wizard"; > + xlnx,speed-grade = <1>; > + clock-names = "clk_in1", "s_axi_aclk"; > + clocks = <&clkc 15>, <&clkc 15>; > + clock-output-names = "clk_out1", "clk_out2", > + "clk_out3", "clk_out4", "clk_out5", > + "clk_out6", "clk_out7"; > + }; > +... > -- > 2.1.1 >
diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml new file mode 100644 index 0000000..a19b9bb --- /dev/null +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx clocking wizard + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> + +description: | + The clocking wizard is a soft ip clocking block of Xilinx versal. It + reads required input clock frequencies from the devicetree and acts as clock + clock output. + +select: false + +properties: + compatible: + - enum: + - xlnx,clocking-wizard + + "#clock-cells": + const: 1 + + clocks: + items: + - description: clock input + - description: axi clock + + clock-names: + items: + - const: clk_in1 + - const: s_axi_aclk + + xlnx,speed-grade: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [1, 2, 3] + description: + Speed grade of the device. + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - speed-grade + +additionalProperties: false + +examples: + - | + clock-generator@40040000 { + #clock-cells = <1>; + reg = <0x40040000 0x1000>; + compatible = "xlnx,clocking-wizard"; + xlnx,speed-grade = <1>; + clock-names = "clk_in1", "s_axi_aclk"; + clocks = <&clkc 15>, <&clkc 15>; + clock-output-names = "clk_out1", "clk_out2", + "clk_out3", "clk_out4", "clk_out5", + "clk_out6", "clk_out7"; + }; +...
Add the devicetree binding for the xilinx clocking wizard. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> --- v6: Fix a yaml warning v7: Add vendor prefix speed-grade .../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml