Message ID | 20201027164208.10026-15-anshuman.gupta@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | HDCP 2.2 and HDCP 1.4 Gen12 DP MST support | expand |
On 2020-10-27 at 22:12:06 +0530, Anshuman Gupta wrote: > Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS > and HDCP2_AUTH_STREAM register in i915_reg header. Reviewed-by: Ramalingam C <ramalingam.c@intel.com> > > Cc: Ramalingam C <ramalingam.c@intel.com> > Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 77461cde6549..c9678c77883d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9894,6 +9894,7 @@ enum skl_power_gate { > _PORTD_HDCP2_BASE, \ > _PORTE_HDCP2_BASE, \ > _PORTF_HDCP2_BASE) + (x)) > + > #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98) > #define _TRANSA_HDCP2_AUTH 0x66498 > #define _TRANSB_HDCP2_AUTH 0x66598 > @@ -9933,6 +9934,35 @@ enum skl_power_gate { > TRANS_HDCP2_STATUS(trans) : \ > PORT_HDCP2_STATUS(port)) > > +#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0) > +#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0 > +#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0 > +#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \ > + _TRANSA_HDCP2_STREAM_STATUS, \ > + _TRANSB_HDCP2_STREAM_STATUS) > +#define STREAM_ENCRYPTION_STATUS BIT(31) > +#define STREAM_TYPE_STATUS BIT(30) > +#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \ > + (INTEL_GEN(dev_priv) >= 12 ? \ > + TRANS_HDCP2_STREAM_STATUS(trans) : \ > + PORT_HDCP2_STREAM_STATUS(port)) > + > +#define _PORTA_HDCP2_AUTH_STREAM 0x66F00 > +#define _PORTB_HDCP2_AUTH_STREAM 0x66F04 > +#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \ > + _PORTA_HDCP2_AUTH_STREAM, \ > + _PORTB_HDCP2_AUTH_STREAM) > +#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00 > +#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04 > +#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \ > + _TRANSA_HDCP2_AUTH_STREAM, \ > + _TRANSB_HDCP2_AUTH_STREAM) > +#define AUTH_STREAM_TYPE BIT(31) > +#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \ > + (INTEL_GEN(dev_priv) >= 12 ? \ > + TRANS_HDCP2_AUTH_STREAM(trans) : \ > + PORT_HDCP2_AUTH_STREAM(port)) > + > /* Per-pipe DDI Function Control */ > #define _TRANS_DDI_FUNC_CTL_A 0x60400 > #define _TRANS_DDI_FUNC_CTL_B 0x61400 > -- > 2.26.2 >
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 77461cde6549..c9678c77883d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9894,6 +9894,7 @@ enum skl_power_gate { _PORTD_HDCP2_BASE, \ _PORTE_HDCP2_BASE, \ _PORTF_HDCP2_BASE) + (x)) + #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98) #define _TRANSA_HDCP2_AUTH 0x66498 #define _TRANSB_HDCP2_AUTH 0x66598 @@ -9933,6 +9934,35 @@ enum skl_power_gate { TRANS_HDCP2_STATUS(trans) : \ PORT_HDCP2_STATUS(port)) +#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0) +#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0 +#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0 +#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \ + _TRANSA_HDCP2_STREAM_STATUS, \ + _TRANSB_HDCP2_STREAM_STATUS) +#define STREAM_ENCRYPTION_STATUS BIT(31) +#define STREAM_TYPE_STATUS BIT(30) +#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \ + (INTEL_GEN(dev_priv) >= 12 ? \ + TRANS_HDCP2_STREAM_STATUS(trans) : \ + PORT_HDCP2_STREAM_STATUS(port)) + +#define _PORTA_HDCP2_AUTH_STREAM 0x66F00 +#define _PORTB_HDCP2_AUTH_STREAM 0x66F04 +#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \ + _PORTA_HDCP2_AUTH_STREAM, \ + _PORTB_HDCP2_AUTH_STREAM) +#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00 +#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04 +#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \ + _TRANSA_HDCP2_AUTH_STREAM, \ + _TRANSB_HDCP2_AUTH_STREAM) +#define AUTH_STREAM_TYPE BIT(31) +#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \ + (INTEL_GEN(dev_priv) >= 12 ? \ + TRANS_HDCP2_AUTH_STREAM(trans) : \ + PORT_HDCP2_AUTH_STREAM(port)) + /* Per-pipe DDI Function Control */ #define _TRANS_DDI_FUNC_CTL_A 0x60400 #define _TRANS_DDI_FUNC_CTL_B 0x61400