| Message ID | 20201104164923.21238-7-digetx@gmail.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Delegated to: | Chanwoo Choi |
| Headers | show |
| Series | Introduce memory interconnect for NVIDIA Tegra SoCs | expand |
On Wed, Nov 04, 2020 at 07:48:42PM +0300, Dmitry Osipenko wrote: > Memory controller is interconnected with memory clients and with the > External Memory Controller. Document new interconnect property which > turns memory controller into interconnect provider. > > Acked-by: Rob Herring <robh@kernel.org> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../bindings/memory-controllers/nvidia,tegra20-mc.txt | 3 +++ Thanks, applied. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt index e55328237df4..739b7c6f2e26 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt @@ -16,6 +16,8 @@ Required properties: IOMMU specifier needed to encode an address. GART supports only a single address space that is shared by all devices, therefore no additional information needed for the address encoding. +- #interconnect-cells : Should be 1. This cell represents memory client. + The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>. Example: mc: memory-controller@7000f000 { @@ -27,6 +29,7 @@ Example: interrupts = <GIC_SPI 77 0x04>; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; video-codec@6001a000 {