| Message ID | 20201104164923.21238-11-digetx@gmail.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Delegated to: | Chanwoo Choi |
| Headers | show |
| Series | Introduce memory interconnect for NVIDIA Tegra SoCs | expand |
On Wed, Nov 04, 2020 at 07:48:46PM +0300, Dmitry Osipenko wrote: > External memory controller is interconnected with memory controller and > with external memory. Document new interconnect property which turns > External Memory Controller into interconnect provider. > > Acked-by: Rob Herring <robh@kernel.org> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > .../bindings/memory-controllers/nvidia,tegra30-emc.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) Thanks, applied. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml index 112bae2fcbbd..c243986db420 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -31,6 +31,9 @@ properties: interrupts: maxItems: 1 + "#interconnect-cells": + const: 0 + nvidia,memory-controller: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -214,6 +217,7 @@ required: - interrupts - clocks - nvidia,memory-controller + - "#interconnect-cells" additionalProperties: false @@ -227,6 +231,8 @@ examples: nvidia,memory-controller = <&mc>; + #interconnect-cells = <0>; + emc-timings-1 { nvidia,ram-code = <1>;