diff mbox series

amdgpu/test: deadlock test for CZ family and RV family

Message ID 20201112153536.85696-1-rajib.mahapatra@amd.com (mailing list archive)
State New, archived
Headers show
Series amdgpu/test: deadlock test for CZ family and RV family | expand

Commit Message

rajib.mahapatra@amd.com Nov. 12, 2020, 3:35 p.m. UTC
From: Rajib Mahapatra <Rajib.Mahapatra@amd.com>

It enables the test for RV2 and PCO, whole GPU reset is not supported
for others.

Signed-off-by: Rajib Mahapatra <Rajib.Mahapatra@amd.com>
Change-Id: Id51605d07b334ecea7a88b3c95fdd57008a4458d
---
 include/drm/amdgpu_drm.h      | 15 +++++++++++++++
 tests/amdgpu/deadlock_tests.c | 18 ++++++++++++++++--
 2 files changed, 31 insertions(+), 2 deletions(-)

Comments

Andrey Grodzovsky Nov. 12, 2020, 4:04 p.m. UTC | #1
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>

Andrey

On 11/12/20 10:35 AM, rajib.mahapatra@amd.com wrote:
> From: Rajib Mahapatra <Rajib.Mahapatra@amd.com>
>
> It enables the test for RV2 and PCO, whole GPU reset is not supported
> for others.
>
> Signed-off-by: Rajib Mahapatra <Rajib.Mahapatra@amd.com>
> Change-Id: Id51605d07b334ecea7a88b3c95fdd57008a4458d
> ---
>   include/drm/amdgpu_drm.h      | 15 +++++++++++++++
>   tests/amdgpu/deadlock_tests.c | 18 ++++++++++++++++--
>   2 files changed, 31 insertions(+), 2 deletions(-)
>
> diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
> index be84e43c..bb7ded25 100644
> --- a/include/drm/amdgpu_drm.h
> +++ b/include/drm/amdgpu_drm.h
> @@ -995,6 +995,21 @@ struct drm_amdgpu_info_vce_clock_table {
>   #define AMDGPU_FAMILY_AI			141 /* Vega10 */
>   #define AMDGPU_FAMILY_RV			142 /* Raven */
>   
> +/*
> + * Asic Rev
> + */
> +#define RAVEN_A0 0x01
> +#define PICASSO_A0 0x41
> +
> +#define RAVEN2_A0 0x81
> +#define RAVEN_UNKNOWN 0xFF
> +
> +#define PICASSO_15D8_REV_E3 0xE3
> +
> +#define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
> +#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
> +#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < PICASSO_15D8_REV_E3))
> +
>   #if defined(__cplusplus)
>   }
>   #endif
> diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
> index a6c2635d..3be99dc8 100644
> --- a/tests/amdgpu/deadlock_tests.c
> +++ b/tests/amdgpu/deadlock_tests.c
> @@ -126,8 +126,22 @@ CU_BOOL suite_deadlock_tests_enable(void)
>   	if (device_handle->info.family_id != AMDGPU_FAMILY_VI &&
>   	    device_handle->info.family_id != AMDGPU_FAMILY_AI &&
>   	    device_handle->info.family_id != AMDGPU_FAMILY_CI) {
> -		printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n");
> -		enable = CU_FALSE;
> +		if (device_handle->info.family_id == AMDGPU_FAMILY_CZ) {
> +			printf("\n\nWhole GPU reset is not supported for the ASIC, deadlock suite disabled\n");Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
> +			enable = CU_FALSE;
> +		} else if (device_handle->info.family_id == AMDGPU_FAMILY_RV) {
> +			if (ASICREV_IS_RAVEN2(device_handle->info.chip_external_rev)) {
> +				enable = CU_TRUE;
> +			} else if (ASICREV_IS_PICASSO(device_handle->info.chip_external_rev)) {
> +				enable = CU_TRUE;
> +			} else {
> +				printf("\n\nWhole GPU reset is not supported for the ASIC, deadlock suite disabled\n");
> +				enable = CU_FALSE;
> +			}
> +		} else {
> +			printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n");
> +			enable = CU_FALSE;
> +		}
>   	}
>   
>   	if (device_handle->info.family_id >= AMDGPU_FAMILY_AI)
Alex Deucher Nov. 12, 2020, 8:17 p.m. UTC | #2
On Thu, Nov 12, 2020 at 10:36 AM <rajib.mahapatra@amd.com> wrote:
>
> From: Rajib Mahapatra <Rajib.Mahapatra@amd.com>
>
> It enables the test for RV2 and PCO, whole GPU reset is not supported
> for others.
>
> Signed-off-by: Rajib Mahapatra <Rajib.Mahapatra@amd.com>
> Change-Id: Id51605d07b334ecea7a88b3c95fdd57008a4458d

libdrm uses gltlab merge requests.  Please file a gitlab MR for the change:
https://gitlab.freedesktop.org/mesa/drm/-/merge_requests

Alex

> ---
>  include/drm/amdgpu_drm.h      | 15 +++++++++++++++
>  tests/amdgpu/deadlock_tests.c | 18 ++++++++++++++++--
>  2 files changed, 31 insertions(+), 2 deletions(-)
>
> diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
> index be84e43c..bb7ded25 100644
> --- a/include/drm/amdgpu_drm.h
> +++ b/include/drm/amdgpu_drm.h
> @@ -995,6 +995,21 @@ struct drm_amdgpu_info_vce_clock_table {
>  #define AMDGPU_FAMILY_AI                       141 /* Vega10 */
>  #define AMDGPU_FAMILY_RV                       142 /* Raven */
>
> +/*
> + * Asic Rev
> + */
> +#define RAVEN_A0 0x01
> +#define PICASSO_A0 0x41
> +
> +#define RAVEN2_A0 0x81
> +#define RAVEN_UNKNOWN 0xFF
> +
> +#define PICASSO_15D8_REV_E3 0xE3
> +
> +#define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
> +#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
> +#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < PICASSO_15D8_REV_E3))
> +
>  #if defined(__cplusplus)
>  }
>  #endif
> diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
> index a6c2635d..3be99dc8 100644
> --- a/tests/amdgpu/deadlock_tests.c
> +++ b/tests/amdgpu/deadlock_tests.c
> @@ -126,8 +126,22 @@ CU_BOOL suite_deadlock_tests_enable(void)
>         if (device_handle->info.family_id != AMDGPU_FAMILY_VI &&
>             device_handle->info.family_id != AMDGPU_FAMILY_AI &&
>             device_handle->info.family_id != AMDGPU_FAMILY_CI) {
> -               printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n");
> -               enable = CU_FALSE;
> +               if (device_handle->info.family_id == AMDGPU_FAMILY_CZ) {
> +                       printf("\n\nWhole GPU reset is not supported for the ASIC, deadlock suite disabled\n");
> +                       enable = CU_FALSE;
> +               } else if (device_handle->info.family_id == AMDGPU_FAMILY_RV) {
> +                       if (ASICREV_IS_RAVEN2(device_handle->info.chip_external_rev)) {
> +                               enable = CU_TRUE;
> +                       } else if (ASICREV_IS_PICASSO(device_handle->info.chip_external_rev)) {
> +                               enable = CU_TRUE;
> +                       } else {
> +                               printf("\n\nWhole GPU reset is not supported for the ASIC, deadlock suite disabled\n");
> +                               enable = CU_FALSE;
> +                       }
> +               } else {
> +                       printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n");
> +                       enable = CU_FALSE;
> +               }
>         }
>
>         if (device_handle->info.family_id >= AMDGPU_FAMILY_AI)
> --
> 2.17.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff mbox series

Patch

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index be84e43c..bb7ded25 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -995,6 +995,21 @@  struct drm_amdgpu_info_vce_clock_table {
 #define AMDGPU_FAMILY_AI			141 /* Vega10 */
 #define AMDGPU_FAMILY_RV			142 /* Raven */
 
+/*
+ * Asic Rev
+ */
+#define RAVEN_A0 0x01
+#define PICASSO_A0 0x41
+
+#define RAVEN2_A0 0x81
+#define RAVEN_UNKNOWN 0xFF
+
+#define PICASSO_15D8_REV_E3 0xE3
+
+#define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
+#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
+#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < PICASSO_15D8_REV_E3))
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
index a6c2635d..3be99dc8 100644
--- a/tests/amdgpu/deadlock_tests.c
+++ b/tests/amdgpu/deadlock_tests.c
@@ -126,8 +126,22 @@  CU_BOOL suite_deadlock_tests_enable(void)
 	if (device_handle->info.family_id != AMDGPU_FAMILY_VI &&
 	    device_handle->info.family_id != AMDGPU_FAMILY_AI &&
 	    device_handle->info.family_id != AMDGPU_FAMILY_CI) {
-		printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n");
-		enable = CU_FALSE;
+		if (device_handle->info.family_id == AMDGPU_FAMILY_CZ) {
+			printf("\n\nWhole GPU reset is not supported for the ASIC, deadlock suite disabled\n");
+			enable = CU_FALSE;
+		} else if (device_handle->info.family_id == AMDGPU_FAMILY_RV) {
+			if (ASICREV_IS_RAVEN2(device_handle->info.chip_external_rev)) {
+				enable = CU_TRUE;
+			} else if (ASICREV_IS_PICASSO(device_handle->info.chip_external_rev)) {
+				enable = CU_TRUE;
+			} else {
+				printf("\n\nWhole GPU reset is not supported for the ASIC, deadlock suite disabled\n");
+				enable = CU_FALSE;
+			}
+		} else {
+			printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n");
+			enable = CU_FALSE;
+		}
 	}
 
 	if (device_handle->info.family_id >= AMDGPU_FAMILY_AI)