| Message ID | 20201104080539.3205889-2-ito-yuichi@fujitsu.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable support IPI_CPU_CRASH_STOP to be pseudo-NMI | expand |
Hi Yuichi-san, This patch is under review here: https://lore.kernel.org/linux-arm-kernel/1604317487-14543-3-git-send-email-sumit.garg@linaro.org/ So, it would be great if you could send your feedback to the thread; testing, code review. Thanks, Masa On Wed, Nov 04, 2020 at 05:05:37PM +0900, Yuichi Ito wrote: > From: From: Sumit Garg <sumit.garg@linaro.org> > > Add support to handle SGIs as pseudo NMIs. As SGIs or IPIs default to a > special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI > handler update in case of SGIs. > > Also, enable NMI support prior to gic_smp_init() as allocation of SGIs > as IRQs/NMIs happen as part of this routine. > > Signed-off-by: Sumit Garg <sumit.garg@linaro.org> > --- > drivers/irqchip/irq-gic-v3.c | 29 +++++++++++++++++++++-------- > 1 file changed, 21 insertions(+), 8 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 16fecc0..7010ae2 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -461,6 +461,7 @@ static u32 gic_get_ppi_index(struct irq_data *d) > static int gic_irq_nmi_setup(struct irq_data *d) > { > struct irq_desc *desc = irq_to_desc(d->irq); > + u32 idx; > > if (!gic_supports_nmi()) > return -EINVAL; > @@ -478,16 +479,22 @@ static int gic_irq_nmi_setup(struct irq_data *d) > return -EINVAL; > > /* desc lock should already be held */ > - if (gic_irq_in_rdist(d)) { > - u32 idx = gic_get_ppi_index(d); > + switch (get_intid_range(d)) { > + case SGI_RANGE: > + break; > + case PPI_RANGE: > + case EPPI_RANGE: > + idx = gic_get_ppi_index(d); > > /* Setting up PPI as NMI, only switch handler for first NMI */ > if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { > refcount_set(&ppi_nmi_refs[idx], 1); > desc->handle_irq = handle_percpu_devid_fasteoi_nmi; > } > - } else { > + break; > + default: > desc->handle_irq = handle_fasteoi_nmi; > + break; > } > > gic_irq_set_prio(d, GICD_INT_NMI_PRI); > @@ -498,6 +505,7 @@ static int gic_irq_nmi_setup(struct irq_data *d) > static void gic_irq_nmi_teardown(struct irq_data *d) > { > struct irq_desc *desc = irq_to_desc(d->irq); > + u32 idx; > > if (WARN_ON(!gic_supports_nmi())) > return; > @@ -515,14 +523,20 @@ static void gic_irq_nmi_teardown(struct irq_data *d) > return; > > /* desc lock should already be held */ > - if (gic_irq_in_rdist(d)) { > - u32 idx = gic_get_ppi_index(d); > + switch (get_intid_range(d)) { > + case SGI_RANGE: > + break; > + case PPI_RANGE: > + case EPPI_RANGE: > + idx = gic_get_ppi_index(d); > > /* Tearing down NMI, only switch handler for last NMI */ > if (refcount_dec_and_test(&ppi_nmi_refs[idx])) > desc->handle_irq = handle_percpu_devid_irq; > - } else { > + break; > + default: > desc->handle_irq = handle_fasteoi_irq; > + break; > } > > gic_irq_set_prio(d, GICD_INT_DEF_PRI); > @@ -1708,6 +1722,7 @@ static int __init gic_init_bases(void __iomem *dist_base, > > gic_dist_init(); > gic_cpu_init(); > + gic_enable_nmi_support(); > gic_smp_init(); > gic_cpu_pm_init(); > > @@ -1719,8 +1734,6 @@ static int __init gic_init_bases(void __iomem *dist_base, > gicv2m_init(handle, gic_data.domain); > } > > - gic_enable_nmi_support(); > - > return 0; > > out_free: > -- > 1.8.3.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 16fecc0..7010ae2 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -461,6 +461,7 @@ static u32 gic_get_ppi_index(struct irq_data *d) static int gic_irq_nmi_setup(struct irq_data *d) { struct irq_desc *desc = irq_to_desc(d->irq); + u32 idx; if (!gic_supports_nmi()) return -EINVAL; @@ -478,16 +479,22 @@ static int gic_irq_nmi_setup(struct irq_data *d) return -EINVAL; /* desc lock should already be held */ - if (gic_irq_in_rdist(d)) { - u32 idx = gic_get_ppi_index(d); + switch (get_intid_range(d)) { + case SGI_RANGE: + break; + case PPI_RANGE: + case EPPI_RANGE: + idx = gic_get_ppi_index(d); /* Setting up PPI as NMI, only switch handler for first NMI */ if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { refcount_set(&ppi_nmi_refs[idx], 1); desc->handle_irq = handle_percpu_devid_fasteoi_nmi; } - } else { + break; + default: desc->handle_irq = handle_fasteoi_nmi; + break; } gic_irq_set_prio(d, GICD_INT_NMI_PRI); @@ -498,6 +505,7 @@ static int gic_irq_nmi_setup(struct irq_data *d) static void gic_irq_nmi_teardown(struct irq_data *d) { struct irq_desc *desc = irq_to_desc(d->irq); + u32 idx; if (WARN_ON(!gic_supports_nmi())) return; @@ -515,14 +523,20 @@ static void gic_irq_nmi_teardown(struct irq_data *d) return; /* desc lock should already be held */ - if (gic_irq_in_rdist(d)) { - u32 idx = gic_get_ppi_index(d); + switch (get_intid_range(d)) { + case SGI_RANGE: + break; + case PPI_RANGE: + case EPPI_RANGE: + idx = gic_get_ppi_index(d); /* Tearing down NMI, only switch handler for last NMI */ if (refcount_dec_and_test(&ppi_nmi_refs[idx])) desc->handle_irq = handle_percpu_devid_irq; - } else { + break; + default: desc->handle_irq = handle_fasteoi_irq; + break; } gic_irq_set_prio(d, GICD_INT_DEF_PRI); @@ -1708,6 +1722,7 @@ static int __init gic_init_bases(void __iomem *dist_base, gic_dist_init(); gic_cpu_init(); + gic_enable_nmi_support(); gic_smp_init(); gic_cpu_pm_init(); @@ -1719,8 +1734,6 @@ static int __init gic_init_bases(void __iomem *dist_base, gicv2m_init(handle, gic_data.domain); } - gic_enable_nmi_support(); - return 0; out_free: