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[RFC,2/2] arm64: Expose EPAN support via HWCAPS2_EPAN

Message ID 20201113152023.102855-3-vladimir.murzin@arm.com (mailing list archive)
State New, archived
Headers show
Series arm64: Support Enhanced PAN | expand

Commit Message

Vladimir Murzin Nov. 13, 2020, 3:20 p.m. UTC
So user have a clue whether exec-only permissions will work.

Cc: Kees Cook <keescook@chromium.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
 arch/arm64/include/asm/hwcap.h      | 1 +
 arch/arm64/include/asm/sysreg.h     | 1 +
 arch/arm64/include/uapi/asm/hwcap.h | 1 +
 arch/arm64/kernel/cpufeature.c      | 3 +++
 arch/arm64/kernel/cpuinfo.c         | 1 +
 5 files changed, 7 insertions(+)

Comments

Catalin Marinas Nov. 17, 2020, 4:59 p.m. UTC | #1
On Fri, Nov 13, 2020 at 03:20:23PM +0000, Vladimir Murzin wrote:
> So user have a clue whether exec-only permissions will work.

I do think we should tell user the PROT_EXEC actually gives execute-only
permission.

> --- a/arch/arm64/include/uapi/asm/hwcap.h
> +++ b/arch/arm64/include/uapi/asm/hwcap.h
> @@ -75,5 +75,6 @@
>  #define HWCAP2_RNG		(1 << 16)
>  #define HWCAP2_BTI		(1 << 17)
>  #define HWCAP2_MTE		(1 << 18)
> +#define HWCAP2_EPAN		(1 << 19)

However, I wonder whether EPAN is meaningful to the user. PAN is a
kernel protection that doesn't say much from a user perspective. Maybe
something like HWCAP2_EXECONLY?

That said, we do have a precedent on 32-bit where we exposed HWCAP_LPAE
to the user meaning that 64-bit atomics are available.
Vladimir Murzin Nov. 18, 2020, 12:43 p.m. UTC | #2
On 11/17/20 4:59 PM, Catalin Marinas wrote:
> On Fri, Nov 13, 2020 at 03:20:23PM +0000, Vladimir Murzin wrote:
>> So user have a clue whether exec-only permissions will work.
> 
> I do think we should tell user the PROT_EXEC actually gives execute-only
> permission.

Ack.

> 
>> --- a/arch/arm64/include/uapi/asm/hwcap.h
>> +++ b/arch/arm64/include/uapi/asm/hwcap.h
>> @@ -75,5 +75,6 @@
>>  #define HWCAP2_RNG		(1 << 16)
>>  #define HWCAP2_BTI		(1 << 17)
>>  #define HWCAP2_MTE		(1 << 18)
>> +#define HWCAP2_EPAN		(1 << 19)
> 
> However, I wonder whether EPAN is meaningful to the user. PAN is a
> kernel protection that doesn't say much from a user perspective. Maybe
> something like HWCAP2_EXECONLY?

Works for me.

> 
> That said, we do have a precedent on 32-bit where we exposed HWCAP_LPAE
> to the user meaning that 64-bit atomics are available.
> 

It doesn't mean we have to follow it :)

Cheers
Vladimir
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index 9a5498c..6274c6c 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -105,6 +105,7 @@ 
 #define KERNEL_HWCAP_RNG		__khwcap2_feature(RNG)
 #define KERNEL_HWCAP_BTI		__khwcap2_feature(BTI)
 #define KERNEL_HWCAP_MTE		__khwcap2_feature(MTE)
+#define KERNEL_HWCAP_EPAN		__khwcap2_feature(EPAN)
 
 /*
  * This yields a mask that user programs can use to figure out what
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 19147b6..e7bc373 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -796,6 +796,7 @@ 
 
 #define ID_AA64MMFR1_VMIDBITS_8		0
 #define ID_AA64MMFR1_VMIDBITS_16	2
+#define ID_AA64MMFR1_EPAN		3
 
 /* id_aa64mmfr2 */
 #define ID_AA64MMFR2_E0PD_SHIFT		60
diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h
index b8f41aa..a99da14 100644
--- a/arch/arm64/include/uapi/asm/hwcap.h
+++ b/arch/arm64/include/uapi/asm/hwcap.h
@@ -75,5 +75,6 @@ 
 #define HWCAP2_RNG		(1 << 16)
 #define HWCAP2_BTI		(1 << 17)
 #define HWCAP2_MTE		(1 << 18)
+#define HWCAP2_EPAN		(1 << 19)
 
 #endif /* _UAPI__ASM_HWCAP_H */
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 2033e0b..bb2016c 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2275,6 +2275,9 @@  static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 #ifdef CONFIG_ARM64_MTE
 	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
 #endif /* CONFIG_ARM64_MTE */
+#ifdef CONFIG_ARM64_EPAN
+	HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_PAN_SHIFT, FTR_UNSIGNED, ID_AA64MMFR1_EPAN, CAP_HWCAP, KERNEL_HWCAP_EPAN),
+#endif
 	{},
 };
 
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 77605ae..9b69b13 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -94,6 +94,7 @@  static const char *const hwcap_str[] = {
 	[KERNEL_HWCAP_RNG]		= "rng",
 	[KERNEL_HWCAP_BTI]		= "bti",
 	[KERNEL_HWCAP_MTE]		= "mte",
+	[KERNEL_HWCAP_EPAN]		= "epan",
 };
 
 #ifdef CONFIG_COMPAT