| Message ID | 20201101100657.12087-2-ankit.k.nautiyal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for DP-HDMI2.1 PCON | expand |
> -----Original Message----- > From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com> > Sent: Sunday, November 1, 2020 3:37 PM > To: intel-gfx@lists.freedesktop.org > Cc: dri-devel@lists.freedesktop.org; Shankar, Uma <uma.shankar@intel.com>; > Kulkarni, Vandita <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com; > Sharma, Swati2 <swati2.sharma@intel.com> > Subject: [PATCH v2 01/13] drm/edid: Add additional HFVSDB fields for HDMI2.1 > > From: Swati Sharma <swati2.sharma@intel.com> > > The HDMI2.1 extends HFVSDB (HDMI Forum Vendor Specific Data block) to have > fields related to newly defined methods of FRL (Fixed Rate Link) levels, number > of lanes supported, DSC Color bit depth, VRR min/max, FVA (Fast Vactive), ALLM > etc. > > This patch adds the new HFVSDB fields that are required for HDMI2.1. > > v2: Minor fixes + consistent naming for DPCD register masks (Uma Shankar) Looks Good to me. Reviewed-by: Uma Shankar <uma.shankar@intel.com> > Signed-off-by: Sharma, Swati2 <swati2.sharma@intel.com> > Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > --- > include/drm/drm_edid.h | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index > b27a0e2169c8..a6ca992e105d 100644 > --- a/include/drm/drm_edid.h > +++ b/include/drm/drm_edid.h > @@ -229,6 +229,36 @@ struct detailed_timing { > DRM_EDID_YCBCR420_DC_36 | \ > DRM_EDID_YCBCR420_DC_30) > > +/* HDMI 2.1 additional fields */ > +#define DRM_EDID_MAX_FRL_RATE_MASK 0xf0 > +#define DRM_EDID_FAPA_START_LOCATION (1 << 0) > +#define DRM_EDID_ALLM (1 << 1) > +#define DRM_EDID_FVA (1 << 2) > + > +/* Deep Color specific */ > +#define DRM_EDID_DC_30BIT_420 (1 << 0) > +#define DRM_EDID_DC_36BIT_420 (1 << 1) > +#define DRM_EDID_DC_48BIT_420 (1 << 2) > + > +/* VRR specific */ > +#define DRM_EDID_CNMVRR (1 << 3) > +#define DRM_EDID_CINEMA_VRR (1 << 4) > +#define DRM_EDID_MDELTA (1 << 5) > +#define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0 > +#define DRM_EDID_VRR_MAX_LOWER_MASK 0xff > +#define DRM_EDID_VRR_MIN_MASK 0x3f > + > +/* DSC specific */ > +#define DRM_EDID_DSC_10BPC (1 << 0) > +#define DRM_EDID_DSC_12BPC (1 << 1) > +#define DRM_EDID_DSC_16BPC (1 << 2) > +#define DRM_EDID_DSC_ALL_BPP (1 << 3) > +#define DRM_EDID_DSC_NATIVE_420 (1 << 6) > +#define DRM_EDID_DSC_1P2 (1 << 7) > +#define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0 > +#define DRM_EDID_DSC_MAX_SLICES 0xf > +#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f > + > /* ELD Header Block */ > #define DRM_ELD_HEADER_BLOCK_SIZE 4 > > -- > 2.17.1
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index b27a0e2169c8..a6ca992e105d 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -229,6 +229,36 @@ struct detailed_timing { DRM_EDID_YCBCR420_DC_36 | \ DRM_EDID_YCBCR420_DC_30) +/* HDMI 2.1 additional fields */ +#define DRM_EDID_MAX_FRL_RATE_MASK 0xf0 +#define DRM_EDID_FAPA_START_LOCATION (1 << 0) +#define DRM_EDID_ALLM (1 << 1) +#define DRM_EDID_FVA (1 << 2) + +/* Deep Color specific */ +#define DRM_EDID_DC_30BIT_420 (1 << 0) +#define DRM_EDID_DC_36BIT_420 (1 << 1) +#define DRM_EDID_DC_48BIT_420 (1 << 2) + +/* VRR specific */ +#define DRM_EDID_CNMVRR (1 << 3) +#define DRM_EDID_CINEMA_VRR (1 << 4) +#define DRM_EDID_MDELTA (1 << 5) +#define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0 +#define DRM_EDID_VRR_MAX_LOWER_MASK 0xff +#define DRM_EDID_VRR_MIN_MASK 0x3f + +/* DSC specific */ +#define DRM_EDID_DSC_10BPC (1 << 0) +#define DRM_EDID_DSC_12BPC (1 << 1) +#define DRM_EDID_DSC_16BPC (1 << 2) +#define DRM_EDID_DSC_ALL_BPP (1 << 3) +#define DRM_EDID_DSC_NATIVE_420 (1 << 6) +#define DRM_EDID_DSC_1P2 (1 << 7) +#define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0 +#define DRM_EDID_DSC_MAX_SLICES 0xf +#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f + /* ELD Header Block */ #define DRM_ELD_HEADER_BLOCK_SIZE 4