diff mbox series

[1/3] ARM: dts: sun8i: v3s: add EHCI/OHCI0 device nodes

Message ID 20201122003841.1957034-2-icenowy@aosc.io (mailing list archive)
State New, archived
Headers show
Series ARM: dts: sun8i: v3s: enable EHCI/OHCI | expand

Commit Message

Icenowy Zheng Nov. 22, 2020, 12:38 a.m. UTC 
The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
controllers.

Add the device nodes for the controllers.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

Comments

Chen-Yu Tsai Nov. 23, 2020, 3:38 a.m. UTC | #1 
On Sun, Nov 22, 2020 at 8:39 AM Icenowy Zheng <icenowy@aosc.io> wrote:
>
> The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
> controllers.
>
> Add the device nodes for the controllers.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Acked-by: Chen-Yu Tsai <wens@csie.org>
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 7b2d684aeb97..3e7e99745b73 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -297,6 +297,25 @@  usbphy: phy@1c19400 {
 			#phy-cells = <1>;
 		};
 
+		ehci0: usb@1c1a000 {
+			compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
+			reg = <0x01c1a000 0x100>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
+			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+			status = "disabled";
+		};
+
+		ohci0: usb@1c1a400 {
+			compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
+			reg = <0x01c1a400 0x100>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+			status = "disabled";
+		};
+
 		ccu: clock@1c20000 {
 			compatible = "allwinner,sun8i-v3s-ccu";
 			reg = <0x01c20000 0x400>;