| Message ID | 20201120144245.398711-3-maxime@cerno.tech (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/vc4: Rework the HVS muxing code | expand |
Am 20.11.20 um 15:42 schrieb Maxime Ripard: > The current HVS muxing code will consider the CRTCs in a given state to > setup their muxing in the HVS, and disable the other CRTCs muxes. > > However, it's valid to only update a single CRTC with a state, and in this > situation we would mux out a CRTC that was enabled but left untouched by > the new state. > > Fix this by setting a flag on the CRTC state when the muxing has been > changed, and only change the muxing configuration when that flag is there. > > Fixes: 87ebcd42fb7b ("drm/vc4: crtc: Assign output to channel automatically") > Reviewed-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> > Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> > Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> > --- > drivers/gpu/drm/vc4/vc4_drv.h | 3 ++ > drivers/gpu/drm/vc4/vc4_kms.c | 81 +++++++++++++++++++---------------- > 2 files changed, 48 insertions(+), 36 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h > index fcfeef0949af..c5f2944d5bc6 100644 > --- a/drivers/gpu/drm/vc4/vc4_drv.h > +++ b/drivers/gpu/drm/vc4/vc4_drv.h > @@ -532,6 +532,9 @@ struct vc4_crtc_state { > unsigned int top; > unsigned int bottom; > } margins; > + > + /* Transitional state below, only valid during atomic commits */ > + bool update_muxing; > }; > > #define VC4_HVS_CHANNEL_DISABLED ((unsigned int)-1) > diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c > index 0bbd7b554275..ba310c0ab5f6 100644 > --- a/drivers/gpu/drm/vc4/vc4_kms.c > +++ b/drivers/gpu/drm/vc4/vc4_kms.c > @@ -239,10 +239,7 @@ static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4, > { > struct drm_crtc_state *crtc_state; > struct drm_crtc *crtc; > - unsigned char dsp2_mux = 0; > - unsigned char dsp3_mux = 3; > - unsigned char dsp4_mux = 3; > - unsigned char dsp5_mux = 3; > + unsigned char mux; > unsigned int i; > u32 reg; > > @@ -250,50 +247,59 @@ static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4, > struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); > struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); > > - if (!crtc_state->active) > + if (!vc4_state->update_muxing) > continue; > > switch (vc4_crtc->data->hvs_output) { > case 2: > - dsp2_mux = (vc4_state->assigned_channel == 2) ? 0 : 1; > + mux = (vc4_state->assigned_channel == 2) ? 0 : 1; > + reg = HVS_READ(SCALER_DISPECTRL); > + HVS_WRITE(SCALER_DISPECTRL, > + (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) | > + VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX)); > break; > > case 3: > - dsp3_mux = vc4_state->assigned_channel; > + if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) > + mux = 3; > + else > + mux = vc4_state->assigned_channel; > + > + reg = HVS_READ(SCALER_DISPCTRL); > + HVS_WRITE(SCALER_DISPCTRL, > + (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) | > + VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX)); > break; > > case 4: > - dsp4_mux = vc4_state->assigned_channel; > + if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) > + mux = 3; > + else > + mux = vc4_state->assigned_channel; > + > + reg = HVS_READ(SCALER_DISPEOLN); > + HVS_WRITE(SCALER_DISPEOLN, > + (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) | > + VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX)); > + > break; > > case 5: > - dsp5_mux = vc4_state->assigned_channel; > + if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) > + mux = 3; > + else > + mux = vc4_state->assigned_channel; > + > + reg = HVS_READ(SCALER_DISPDITHER); > + HVS_WRITE(SCALER_DISPDITHER, > + (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) | > + VC4_SET_FIELD(mux, SCALER_DISPDITHER_DSP5_MUX)); > break; > > default: > break; > } > } > - > - reg = HVS_READ(SCALER_DISPECTRL); > - HVS_WRITE(SCALER_DISPECTRL, > - (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) | > - VC4_SET_FIELD(dsp2_mux, SCALER_DISPECTRL_DSP2_MUX)); > - > - reg = HVS_READ(SCALER_DISPCTRL); > - HVS_WRITE(SCALER_DISPCTRL, > - (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) | > - VC4_SET_FIELD(dsp3_mux, SCALER_DISPCTRL_DSP3_MUX)); > - > - reg = HVS_READ(SCALER_DISPEOLN); > - HVS_WRITE(SCALER_DISPEOLN, > - (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) | > - VC4_SET_FIELD(dsp4_mux, SCALER_DISPEOLN_DSP4_MUX)); > - > - reg = HVS_READ(SCALER_DISPDITHER); > - HVS_WRITE(SCALER_DISPDITHER, > - (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) | > - VC4_SET_FIELD(dsp5_mux, SCALER_DISPDITHER_DSP5_MUX)); > } > > static void > @@ -789,17 +795,20 @@ static int vc4_pv_muxing_atomic_check(struct drm_device *dev, > struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); > unsigned int matching_channels; > > - if (old_crtc_state->enable && !new_crtc_state->enable) { > + /* Nothing to do here, let's skip it */ > + if (old_crtc_state->enable == new_crtc_state->enable) > + continue; > + > + /* Muxing will need to be modified, mark it as such */ > + new_vc4_crtc_state->update_muxing = true; > + > + /* If we're disabling our CRTC, we put back our channel */ > + if (!new_crtc_state->enable) { > hvs_new_state->unassigned_channels |= BIT(old_vc4_crtc_state->assigned_channel); > new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; > + continue; > } > > - if (!new_crtc_state->enable) > - continue; > - > - if (new_vc4_crtc_state->assigned_channel != VC4_HVS_CHANNEL_DISABLED) > - continue; > - > /* > * The problem we have to solve here is that we have > * up to 7 encoders, connected to up to 6 CRTCs. >
On Mon, Nov 23, 2020 at 08:50:49AM +0100, Thomas Zimmermann wrote: > > > Am 20.11.20 um 15:42 schrieb Maxime Ripard: > > The current HVS muxing code will consider the CRTCs in a given state to > > setup their muxing in the HVS, and disable the other CRTCs muxes. > > > > However, it's valid to only update a single CRTC with a state, and in this > > situation we would mux out a CRTC that was enabled but left untouched by > > the new state. > > > > Fix this by setting a flag on the CRTC state when the muxing has been > > changed, and only change the muxing configuration when that flag is there. > > > > Fixes: 87ebcd42fb7b ("drm/vc4: crtc: Assign output to channel automatically") > > Reviewed-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> > > Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> > > Signed-off-by: Maxime Ripard <maxime@cerno.tech> > > Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Applied both, thanks! Maxime
diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index fcfeef0949af..c5f2944d5bc6 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -532,6 +532,9 @@ struct vc4_crtc_state { unsigned int top; unsigned int bottom; } margins; + + /* Transitional state below, only valid during atomic commits */ + bool update_muxing; }; #define VC4_HVS_CHANNEL_DISABLED ((unsigned int)-1) diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c index 0bbd7b554275..ba310c0ab5f6 100644 --- a/drivers/gpu/drm/vc4/vc4_kms.c +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -239,10 +239,7 @@ static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4, { struct drm_crtc_state *crtc_state; struct drm_crtc *crtc; - unsigned char dsp2_mux = 0; - unsigned char dsp3_mux = 3; - unsigned char dsp4_mux = 3; - unsigned char dsp5_mux = 3; + unsigned char mux; unsigned int i; u32 reg; @@ -250,50 +247,59 @@ static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4, struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); - if (!crtc_state->active) + if (!vc4_state->update_muxing) continue; switch (vc4_crtc->data->hvs_output) { case 2: - dsp2_mux = (vc4_state->assigned_channel == 2) ? 0 : 1; + mux = (vc4_state->assigned_channel == 2) ? 0 : 1; + reg = HVS_READ(SCALER_DISPECTRL); + HVS_WRITE(SCALER_DISPECTRL, + (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) | + VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX)); break; case 3: - dsp3_mux = vc4_state->assigned_channel; + if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) + mux = 3; + else + mux = vc4_state->assigned_channel; + + reg = HVS_READ(SCALER_DISPCTRL); + HVS_WRITE(SCALER_DISPCTRL, + (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) | + VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX)); break; case 4: - dsp4_mux = vc4_state->assigned_channel; + if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) + mux = 3; + else + mux = vc4_state->assigned_channel; + + reg = HVS_READ(SCALER_DISPEOLN); + HVS_WRITE(SCALER_DISPEOLN, + (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) | + VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX)); + break; case 5: - dsp5_mux = vc4_state->assigned_channel; + if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) + mux = 3; + else + mux = vc4_state->assigned_channel; + + reg = HVS_READ(SCALER_DISPDITHER); + HVS_WRITE(SCALER_DISPDITHER, + (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) | + VC4_SET_FIELD(mux, SCALER_DISPDITHER_DSP5_MUX)); break; default: break; } } - - reg = HVS_READ(SCALER_DISPECTRL); - HVS_WRITE(SCALER_DISPECTRL, - (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) | - VC4_SET_FIELD(dsp2_mux, SCALER_DISPECTRL_DSP2_MUX)); - - reg = HVS_READ(SCALER_DISPCTRL); - HVS_WRITE(SCALER_DISPCTRL, - (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) | - VC4_SET_FIELD(dsp3_mux, SCALER_DISPCTRL_DSP3_MUX)); - - reg = HVS_READ(SCALER_DISPEOLN); - HVS_WRITE(SCALER_DISPEOLN, - (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) | - VC4_SET_FIELD(dsp4_mux, SCALER_DISPEOLN_DSP4_MUX)); - - reg = HVS_READ(SCALER_DISPDITHER); - HVS_WRITE(SCALER_DISPDITHER, - (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) | - VC4_SET_FIELD(dsp5_mux, SCALER_DISPDITHER_DSP5_MUX)); } static void @@ -789,17 +795,20 @@ static int vc4_pv_muxing_atomic_check(struct drm_device *dev, struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); unsigned int matching_channels; - if (old_crtc_state->enable && !new_crtc_state->enable) { + /* Nothing to do here, let's skip it */ + if (old_crtc_state->enable == new_crtc_state->enable) + continue; + + /* Muxing will need to be modified, mark it as such */ + new_vc4_crtc_state->update_muxing = true; + + /* If we're disabling our CRTC, we put back our channel */ + if (!new_crtc_state->enable) { hvs_new_state->unassigned_channels |= BIT(old_vc4_crtc_state->assigned_channel); new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; + continue; } - if (!new_crtc_state->enable) - continue; - - if (new_vc4_crtc_state->assigned_channel != VC4_HVS_CHANNEL_DISABLED) - continue; - /* * The problem we have to solve here is that we have * up to 7 encoders, connected to up to 6 CRTCs.
The current HVS muxing code will consider the CRTCs in a given state to setup their muxing in the HVS, and disable the other CRTCs muxes. However, it's valid to only update a single CRTC with a state, and in this situation we would mux out a CRTC that was enabled but left untouched by the new state. Fix this by setting a flag on the CRTC state when the muxing has been changed, and only change the muxing configuration when that flag is there. Fixes: 87ebcd42fb7b ("drm/vc4: crtc: Assign output to channel automatically") Reviewed-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> --- drivers/gpu/drm/vc4/vc4_drv.h | 3 ++ drivers/gpu/drm/vc4/vc4_kms.c | 81 +++++++++++++++++++---------------- 2 files changed, 48 insertions(+), 36 deletions(-)