| Message ID | 1b15266045edbcfff2fc3791c88a5390d7bb3185.1604988979.git.frank@allwinnertech.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Second step support for A100 | expand |
On 10/11/2020 06:29, Frank Lee wrote: > From: Yangtao Li <frank@allwinnertech.com> > > The A100 SoC has a DMA controller that supports 8 DMA channels > to and from various peripherals. > > Add a device node for it. > > Signed-off-by: Yangtao Li <frank@allwinnertech.com> > --- > arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi > index cc321c04f121..c34ed8045363 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi > @@ -101,6 +101,18 @@ ccu: clock@3001000 { > #reset-cells = <1>; > }; > > + dma: dma-controller@3002000 { > + compatible = "allwinner,sun50i-a100-dma"; So at it appears to work with the exact same settings in the driver as the H6, we should have that as a compatible fallback: compatible = "allwinner,sun50i-a100-dma", "allwinner,sun50i-h6-dma"; Cheers, Andre > + reg = <0x03002000 0x1000>; > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; > + clock-names = "bus", "mbus"; > + dma-channels = <8>; > + dma-requests = <51>; > + resets = <&ccu RST_BUS_DMA>; > + #dma-cells = <1>; > + }; > + > gic: interrupt-controller@3021000 { > compatible = "arm,gic-400"; > reg = <0x03021000 0x1000>, <0x03022000 0x2000>, >
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi index cc321c04f121..c34ed8045363 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -101,6 +101,18 @@ ccu: clock@3001000 { #reset-cells = <1>; }; + dma: dma-controller@3002000 { + compatible = "allwinner,sun50i-a100-dma"; + reg = <0x03002000 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names = "bus", "mbus"; + dma-channels = <8>; + dma-requests = <51>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + gic: interrupt-controller@3021000 { compatible = "arm,gic-400"; reg = <0x03021000 0x1000>, <0x03022000 0x2000>,