mbox series

[v6,0/2] Re-enable FBC on TGL

Message ID 20201201190406.1752-1-uma.shankar@intel.com (mailing list archive)
Headers show
Series Re-enable FBC on TGL | expand

Message

Shankar, Uma Dec. 1, 2020, 7:04 p.m. UTC 
FBC was disabled on TGL due to random underruns. It has
been determined that FBC will not work reliably with PSR2.
This series re-enables fbc along with taking care of the
PSR2 limitations for TGL.

Bspec: 50422 HSD: 14010260002

v2: Addressed review comments and added bspec links

v3: Addressed Ville's review comments

v4: Change the WA as per Jose's recommendation.

v5: Addressed Jose's review comments.

v6: Added Jose and Ville RB's. Fixed a minor review
comment.

Uma Shankar (2):
  drm/i915/display/tgl: Disable FBC with PSR2
  Revert "drm/i915/display/fbc: Disable fbc by default on TGL"

 drivers/gpu/drm/i915/display/intel_fbc.c | 19 ++++++++++++-------
 drivers/gpu/drm/i915/i915_drv.h          |  1 +
 2 files changed, 13 insertions(+), 7 deletions(-)

Comments

Souza, Jose Dec. 1, 2020, 6:31 p.m. UTC | #1 
LGTM, thanks for doing the changes.

On Wed, 2020-12-02 at 00:34 +0530, Uma Shankar wrote:
> FBC was disabled on TGL due to random underruns. It has
> been determined that FBC will not work reliably with PSR2.
> This series re-enables fbc along with taking care of the
> PSR2 limitations for TGL.
> 
> Bspec: 50422 HSD: 14010260002
> 
> v2: Addressed review comments and added bspec links
> 
> v3: Addressed Ville's review comments
> 
> v4: Change the WA as per Jose's recommendation.
> 
> v5: Addressed Jose's review comments.
> 
> v6: Added Jose and Ville RB's. Fixed a minor review
> comment.
> 
> Uma Shankar (2):
>   drm/i915/display/tgl: Disable FBC with PSR2
>   Revert "drm/i915/display/fbc: Disable fbc by default on TGL"
> 
>  drivers/gpu/drm/i915/display/intel_fbc.c | 19 ++++++++++++-------
>  drivers/gpu/drm/i915/i915_drv.h          |  1 +
>  2 files changed, 13 insertions(+), 7 deletions(-)
>
Shankar, Uma Dec. 2, 2020, 1:09 p.m. UTC | #2 
> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: Wednesday, December 2, 2020 12:01 AM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com
> Subject: Re: [v6 0/2] Re-enable FBC on TGL
> 
> LGTM, thanks for doing the changes.

Pushed the series to dinq.
Thanks Jose and Ville for the review and feedback.

Regards,
Uma Shankar

> On Wed, 2020-12-02 at 00:34 +0530, Uma Shankar wrote:
> > FBC was disabled on TGL due to random underruns. It has been
> > determined that FBC will not work reliably with PSR2.
> > This series re-enables fbc along with taking care of the
> > PSR2 limitations for TGL.
> >
> > Bspec: 50422 HSD: 14010260002
> >
> > v2: Addressed review comments and added bspec links
> >
> > v3: Addressed Ville's review comments
> >
> > v4: Change the WA as per Jose's recommendation.
> >
> > v5: Addressed Jose's review comments.
> >
> > v6: Added Jose and Ville RB's. Fixed a minor review comment.
> >
> > Uma Shankar (2):
> >   drm/i915/display/tgl: Disable FBC with PSR2
> >   Revert "drm/i915/display/fbc: Disable fbc by default on TGL"
> >
> >  drivers/gpu/drm/i915/display/intel_fbc.c | 19 ++++++++++++-------
> >  drivers/gpu/drm/i915/i915_drv.h          |  1 +
> >  2 files changed, 13 insertions(+), 7 deletions(-)
> >
Chris Wilson Dec. 4, 2020, 11:54 a.m. UTC | #3 
Quoting Shankar, Uma (2020-12-02 13:09:34)
> 
> 
> > -----Original Message-----
> > From: Souza, Jose <jose.souza@intel.com>
> > Sent: Wednesday, December 2, 2020 12:01 AM
> > To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
> > Cc: ville.syrjala@linux.intel.com
> > Subject: Re: [v6 0/2] Re-enable FBC on TGL
> > 
> > LGTM, thanks for doing the changes.
> 
> Pushed the series to dinq.
> Thanks Jose and Ville for the review and feedback.

And CI is reporting pipe underruns again, that seem to date back to
re-enabling FBC.
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9441/fi-tgl-y/igt@gem_exec_gttfill@basic.html
-Chris
Saarinen, Jani Dec. 4, 2020, 1:52 p.m. UTC | #4 
Hi, 
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Chris Wilson
> Sent: perjantai 4. joulukuuta 2020 13.55
> To: Shankar, Uma <uma.shankar@intel.com>; Souza, Jose <jose.souza@intel.com>;
> intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [v6 0/2] Re-enable FBC on TGL
> 
> Quoting Shankar, Uma (2020-12-02 13:09:34)
> >
> >
> > > -----Original Message-----
> > > From: Souza, Jose <jose.souza@intel.com>
> > > Sent: Wednesday, December 2, 2020 12:01 AM
> > > To: Shankar, Uma <uma.shankar@intel.com>;
> > > intel-gfx@lists.freedesktop.org
> > > Cc: ville.syrjala@linux.intel.com
> > > Subject: Re: [v6 0/2] Re-enable FBC on TGL
> > >
> > > LGTM, thanks for doing the changes.
> >
> > Pushed the series to dinq.
> > Thanks Jose and Ville for the review and feedback.
> 
> And CI is reporting pipe underruns again, that seem to date back to re-enabling FBC.
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9441/fi-tgl-
> y/igt@gem_exec_gttfill@basic.html
This still old step/ifwi. 

> -Chris
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