| Message ID | 20201202203817.438713-1-jernej.skrabec@siol.net (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | clk: sunxi-ng: Make sure divider tables have sentinel | expand |
Hi, On Wed, Dec 02, 2020 at 09:38:17PM +0100, Jernej Skrabec wrote: > Two clock divider tables are missing sentinel at the end. Effect of that > is that clock framework reads past the last entry. Fix that with adding > sentinel at the end. > > Issue was discovered with KASan. > > Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") > Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Acked-by: Maxime Ripard <mripard@kernel.org> Mike, Stephen, it's the only patch we're going to send your way for this release, could you pick it up directly? Thanks! Maxime
Quoting Jernej Skrabec (2020-12-02 12:38:17) > Two clock divider tables are missing sentinel at the end. Effect of that > is that clock framework reads past the last entry. Fix that with adding > sentinel at the end. > > Issue was discovered with KASan. > > Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") > Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > --- Applied to clk-next
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index 5f66bf879772..149cfde817cb 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -389,6 +389,7 @@ static struct clk_div_table ths_div_table[] = { { .val = 1, .div = 2 }, { .val = 2, .div = 4 }, { .val = 3, .div = 6 }, + { /* Sentinel */ }, }; static const char * const ths_parents[] = { "osc24M" }; static struct ccu_div ths_clk = { diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index 6b636362379e..7e629a4493af 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c @@ -322,6 +322,7 @@ static struct clk_div_table ths_div_table[] = { { .val = 1, .div = 2 }, { .val = 2, .div = 4 }, { .val = 3, .div = 6 }, + { /* Sentinel */ }, }; static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M", 0x074, 0, 2, ths_div_table, BIT(31), 0);
Two clock divider tables are missing sentinel at the end. Effect of that is that clock framework reads past the last entry. Fix that with adding sentinel at the end. Issue was discovered with KASan. Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> --- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 1 + drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 1 + 2 files changed, 2 insertions(+)