| Message ID | 20201117165312.25847-1-vidyas@nvidia.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
| Series | PCI: dwc: Set 32-bit DMA mask for MSI target address allocation | expand |
Hi, Could you please review this patch in the context of the following patch? http://patchwork.ozlabs.org/project/linux-pci/patch/20201124105035.24573-1-vidyas@nvidia.com/ Thanks, Vidya Sagar On 11/17/2020 10:23 PM, Vidya Sagar wrote: > Set DMA mask to 32-bit while allocating the MSI target address so that > the address is usable for both 32-bit and 64-bit MSI capable devices. > Throw a warning if it fails to set the mask to 32-bit to alert that > devices that are only 32-bit MSI capable may not work properly. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > Given the other patch that I've pushed to the MSI sub-system > http://patchwork.ozlabs.org/project/linux-pci/patch/20201117145728.4516-1-vidyas@nvidia.com/ > which is going to catch any mismatch between MSI capability (32-bit) of the > device and system's inability to allocate the required MSI target address, > I'm not sure how much sense is this patch going to be make. But, I can > certainly say that if the memory allocation mechanism gives the addresses > from 64-bit pool by default, this patch at least makes sure that MSI target > address is allocated from 32-bit pool. > > drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 44c2a6572199..e6a230eddf66 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -388,6 +388,14 @@ int dw_pcie_host_init(struct pcie_port *pp) > dw_chained_msi_isr, > pp); > > + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); > + if (!ret) { > + dev_warn(pci->dev, > + "Failed to set DMA mask to 32-bit. " > + "Devices with only 32-bit MSI support" > + " may not work properly\n"); > + } > + > pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, > sizeof(pp->msi_msg), > DMA_FROM_DEVICE, >
On 2020-11-17 16:53, Vidya Sagar wrote: > Set DMA mask to 32-bit while allocating the MSI target address so that > the address is usable for both 32-bit and 64-bit MSI capable devices. > Throw a warning if it fails to set the mask to 32-bit to alert that > devices that are only 32-bit MSI capable may not work properly. This is slightly wacky, but no more so than the rest of the not-DMA shenanigans here... Ultimately it probably is the least-worst way to avoid the issue, so in terms of functionality, Reviewed-by: Robin Murphy <robin.murphy@arm.com> > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> > --- > Given the other patch that I've pushed to the MSI sub-system > http://patchwork.ozlabs.org/project/linux-pci/patch/20201117145728.4516-1-vidyas@nvidia.com/ > which is going to catch any mismatch between MSI capability (32-bit) of the > device and system's inability to allocate the required MSI target address, > I'm not sure how much sense is this patch going to be make. But, I can > certainly say that if the memory allocation mechanism gives the addresses > from 64-bit pool by default, this patch at least makes sure that MSI target > address is allocated from 32-bit pool. Note that this doesn't change where anything is allocated as such, it just means that on systems with most of their RAM above 4GB, those few bytes of private data that you map "for free" will be copied into the SWIOTLB buffer and hog 2KB of its typical 64MB capacity effectively for ever. > drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 44c2a6572199..e6a230eddf66 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -388,6 +388,14 @@ int dw_pcie_host_init(struct pcie_port *pp) > dw_chained_msi_isr, > pp); > > + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); > + if (!ret) { > + dev_warn(pci->dev, > + "Failed to set DMA mask to 32-bit. " > + "Devices with only 32-bit MSI support" > + " may not work properly\n"); > + } Ironically, the only real reason for that dma_set_mask() to ever fail is if the system had no 32-bit addressable memory, in which case you could likely pick any 32-bit doorbell address with impunity, just not via this mechanism (although whether it would be worthwhile is another matter). Robin. > + > pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, > sizeof(pp->msi_msg), > DMA_FROM_DEVICE, >
On Tue, 17 Nov 2020 22:23:12 +0530, Vidya Sagar wrote: > Set DMA mask to 32-bit while allocating the MSI target address so that > the address is usable for both 32-bit and 64-bit MSI capable devices. > Throw a warning if it fails to set the mask to 32-bit to alert that > devices that are only 32-bit MSI capable may not work properly. Applied to pci/dwc, thanks! [1/1] PCI: dwc: Set 32-bit DMA mask for MSI target address allocation https://git.kernel.org/lpieralisi/pci/c/660c486590 Thanks, Lorenzo
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 44c2a6572199..e6a230eddf66 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -388,6 +388,14 @@ int dw_pcie_host_init(struct pcie_port *pp) dw_chained_msi_isr, pp); + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); + if (!ret) { + dev_warn(pci->dev, + "Failed to set DMA mask to 32-bit. " + "Devices with only 32-bit MSI support" + " may not work properly\n"); + } + pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, sizeof(pp->msi_msg), DMA_FROM_DEVICE,
Set DMA mask to 32-bit while allocating the MSI target address so that the address is usable for both 32-bit and 64-bit MSI capable devices. Throw a warning if it fails to set the mask to 32-bit to alert that devices that are only 32-bit MSI capable may not work properly. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- Given the other patch that I've pushed to the MSI sub-system http://patchwork.ozlabs.org/project/linux-pci/patch/20201117145728.4516-1-vidyas@nvidia.com/ which is going to catch any mismatch between MSI capability (32-bit) of the device and system's inability to allocate the required MSI target address, I'm not sure how much sense is this patch going to be make. But, I can certainly say that if the memory allocation mechanism gives the addresses from 64-bit pool by default, this patch at least makes sure that MSI target address is allocated from 32-bit pool. drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++ 1 file changed, 8 insertions(+)