| Message ID | 20201218083726.16427-3-alice.guo@oss.nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v8,1/4] dt-bindings: soc: imx8m: add DT Binding doc for soc unique ID | expand |
On Fri, Dec 18, 2020 at 04:37:25PM +0800, Alice Guo (OSS) wrote: > From: Alice Guo <alice.guo@nxp.com> > > In order to be able to use NVMEM APIs to read soc unique ID, add the > nvmem data cell and name for nvmem-cells to the "soc" node, and add a > nvmem node which provides soc unique ID to efuse@30350000. > > Signed-off-by: Alice Guo <alice.guo@nxp.com> > --- > Changes for v8: > - none > Changes for v7: > - add Reviewed-by What happened with my reviewed-by? Best regards, Krzysztof
> -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: 2020年12月19日 20:17 > To: Alice Guo (OSS) <alice.guo@oss.nxp.com> > Cc: robh+dt@kernel.org; shawnguo@kernel.org; s.hauer@pengutronix.de; > kernel@pengutronix.de; festevam@gmail.com; devicetree@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; dl-linux-imx > <linux-imx@nxp.com> > Subject: Re: [PATCH v8 3/4] arm64: dts: imx8m: add NVMEM provider and > consumer to read soc unique ID > > On Fri, Dec 18, 2020 at 04:37:25PM +0800, Alice Guo (OSS) wrote: > > From: Alice Guo <alice.guo@nxp.com> > > > > In order to be able to use NVMEM APIs to read soc unique ID, add the > > nvmem data cell and name for nvmem-cells to the "soc" node, and add a > > nvmem node which provides soc unique ID to efuse@30350000. > > > > Signed-off-by: Alice Guo <alice.guo@nxp.com> > > --- > > Changes for v8: > > - none > > Changes for v7: > > - add Reviewed-by > > What happened with my reviewed-by? > > Best regards, > Krzysztof Hi, I forgot to add reviewed-by. ☹ Best regards, Alice
On Mon, Dec 21, 2020 at 03:10:52AM +0000, Alice Guo (OSS) wrote: > > > > -----Original Message----- > > From: Krzysztof Kozlowski <krzk@kernel.org> > > Sent: 2020年12月19日 20:17 > > To: Alice Guo (OSS) <alice.guo@oss.nxp.com> > > Cc: robh+dt@kernel.org; shawnguo@kernel.org; s.hauer@pengutronix.de; > > kernel@pengutronix.de; festevam@gmail.com; devicetree@vger.kernel.org; > > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; dl-linux-imx > > <linux-imx@nxp.com> > > Subject: Re: [PATCH v8 3/4] arm64: dts: imx8m: add NVMEM provider and > > consumer to read soc unique ID > > > > On Fri, Dec 18, 2020 at 04:37:25PM +0800, Alice Guo (OSS) wrote: > > > From: Alice Guo <alice.guo@nxp.com> > > > > > > In order to be able to use NVMEM APIs to read soc unique ID, add the > > > nvmem data cell and name for nvmem-cells to the "soc" node, and add a > > > nvmem node which provides soc unique ID to efuse@30350000. > > > > > > Signed-off-by: Alice Guo <alice.guo@nxp.com> > > > --- > > > Changes for v8: > > > - none > > > Changes for v7: > > > - add Reviewed-by > > > > What happened with my reviewed-by? > > > > Best regards, > > Krzysztof > > Hi, > I forgot to add reviewed-by. ☹ It was there already, so you had to remove it for some reason... but you kept the changelog. Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index d457ce815e68..9bee6f1889a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -261,6 +261,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mm_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -518,6 +520,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mm_uid: unique-id@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index db50e6e01ac5..b344fdc16534 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -245,6 +245,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mn_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -531,6 +533,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mn_uid: unique-id@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ec6ac523ecfc..9401e92f1c84 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -222,6 +222,8 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + nvmem-cells = <&imx8mp_uid>; + nvmem-cell-names = "soc_unique_id"; aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; @@ -328,6 +330,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mp_uid: unique-id@420 { + reg = <0x8 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 9b6d9307e5d7..a2a885f1a07a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -291,6 +291,8 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + nvmem-cells = <&imx8mq_uid>; + nvmem-cell-names = "soc_unique_id"; bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; @@ -555,6 +557,10 @@ #address-cells = <1>; #size-cells = <1>; + imx8mq_uid: soc-uid@410 { + reg = <0x4 0x8>; + }; + cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; };